add new IP core for standard Xilinx Aurora cores

fpga/include/villas/fpga/ips/aurora_xilinx.hpp

@@ -0,0 +1,74 @@
+/** Driver for wrapper around standard Xilinx Aurora (xilinx.com:ip:aurora_8b10b)
+ *
+ * @author Steffen Vogel <post@steffenvogel.de>
+ * @copyright 2017-2018, Institute for Automation of Complex Power Systems, EONERC
+ * @license GNU General Public License (version 3)
+ *
+ * VILLASfpga
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *********************************************************************************/
+
+/** @addtogroup fpga VILLASfpga
+ * @{
+ */
+
+#pragma once
+
+#include <villas/fpga/node.hpp>
+
+namespace villas {
+namespace fpga {
+namespace ip {
+
+class AuroraXilinx : public Node {
+public:
+	static constexpr const char* masterPort = "m_axis";
+	static constexpr const char* slavePort = "s_axis";
+
+	const StreamVertex&
+	getDefaultSlavePort() const
+	{ return getSlavePort(slavePort); }
+
+	const StreamVertex&
+	getDefaultMasterPort() const
+	{ return getMasterPort(masterPort); }
+};
+
+
+class AuroraXilinxFactory : public NodeFactory {
+public:
+
+	Core* create()
+	{ return new AuroraXilinx; }
+
+	virtual std::string
+	getName() const
+	{ return "Aurora"; }
+
+	virtual std::string
+	getDescription() const
+	{ return "Xilinx Aurora 8B/10B."; }
+
+	virtual Vlnv
+	getCompatibleVlnv() const
+	{ return {"xilinx.com:ip:aurora_8b10b:"}; }
+
+};
+
+} /* namespace ip */
+} /* namespace fpga */
+} /* namespace villas */
+
+/** @} */

fpga/lib/CMakeLists.txt

@@ -36,6 +36,7 @@ set(SOURCES
 	ips/bram.cpp
 	ips/rtds.cpp
 	ips/aurora.cpp
+	ips/aurora_xilinx.cpp
 	ips/gpio.cpp
 
 	ips/rtds2gpu/rtds2gpu.cpp

fpga/lib/core.cpp

@@ -187,12 +187,10 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
 			}
 		}
 
-
 		json_t* json_memory_view = json_object_get(json_ip, "memory-view");
 		if (json_is_object(json_memory_view)) {
 			logger->debug("Parse memory view of {}", *ip);
 
-
 			// now find all slave address spaces this master can access
 			const char* bus_name;
 			json_t* json_bus;
@@ -210,7 +208,6 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
 
 				ip->busMasterInterfaces[bus_name] = myAddrSpaceId;
 
-
 				const char* instance_name;
 				json_t* json_instance;
 				json_object_foreach(json_bus, instance_name, json_instance) {
@@ -263,6 +260,7 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
 
 	// Start and check IPs now
 	for (auto &ip : configuredIps) {
+		loggerStatic->info("Initializing {}", *ip);
 
 		// Translate all memory blocks that the IP needs to be accessible from
 		// the process and cache in the instance, so this has not to be done at
@@ -288,8 +286,6 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
 			ip->addressTranslations.emplace(memoryBlock, translation);
 		}
 
-		loggerStatic->info("Initializing {}", *ip);
-
 		if (not ip->init()) {
 			loggerStatic->error("Cannot start IP {}", *ip);
 			continue;

fpga/lib/ips/aurora_xilinx.cpp

@@ -0,0 +1,32 @@
+/** Driver for wrapper around standard Xilinx Aurora (xilinx.com:ip:aurora_8b10b)
+ *
+ * @author Steffen Vogel <post@steffenvogel.de>
+ * @copyright 2017-2018, Institute for Automation of Complex Power Systems, EONERC
+ * @license GNU General Public License (version 3)
+ *
+ * VILLASfpga
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *********************************************************************************/
+
+#include <cstdint>
+
+#include <villas/utils.hpp>
+
+#include <villas/fpga/card.hpp>
+#include <villas/fpga/ips/aurora_xilinx.hpp>
+
+using namespace villas::fpga::ip;
+
+static AuroraXilinxFactory auroraFactoryInstance;