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fpga: Add driver for new register interface of axis cache IP
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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47
fpga/include/villas/fpga/ips/axis_cache.hpp
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47
fpga/include/villas/fpga/ips/axis_cache.hpp
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/* Driver for AXI Stream read cache. This module is used to lower latency of
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* a DMA Scatter Gather engine's descriptor fetching. The driver allows for
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* invalidating the cache.
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*
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* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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* SPDX-FileCopyrightText: 2024 Niklas Eiling
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <villas/fpga/node.hpp>
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namespace villas {
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namespace fpga {
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namespace ip {
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class AxisCache : public Node {
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public:
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AxisCache();
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virtual ~AxisCache();
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virtual bool init() override;
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virtual bool check() override;
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void invalidate();
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protected:
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const size_t registerNum = 1;
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const size_t registerSize = 32;
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static constexpr char registerMemory[] = "reg0";
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std::list<MemoryBlockName> getMemoryBlocks() const override {
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return {registerMemory};
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}
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void setRegister(size_t reg, uint32_t value);
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uint32_t getRegister(size_t reg);
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void resetRegister(size_t reg);
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void resetAllRegisters();
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};
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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#ifndef FMT_LEGACY_OSTREAM_FORMATTER
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template <>
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class fmt::formatter<villas::fpga::ip::AxisCache>
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: public fmt::ostream_formatter {};
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#endif
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79
fpga/lib/ips/axis_cache.cpp
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79
fpga/lib/ips/axis_cache.cpp
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/* Driver for AXI Stream read cache. This module is used to lower latency of
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* a DMA Scatter Gather engine's descriptor fetching. The driver allows for
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* invalidating the cache.
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*
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* Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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* SPDX-FileCopyrightText: 2024 Niklas Eiling
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xilinx/xil_io.h>
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#include <villas/fpga/ips/axis_cache.hpp>
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using namespace villas::fpga::ip;
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#define REGISTER_OUT(NUM) (4 * NUM)
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AxisCache::AxisCache() : Node() {}
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bool AxisCache::init() { return true; }
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bool AxisCache::check() {
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logger->debug("Checking register interface: Base address: 0x{:08x}",
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getBaseAddr(registerMemory));
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uint32_t buf;
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// we shouldn't change the rate register, because this can lead to hardware fault, so start at 1
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for (size_t i = 1; i < registerNum; i++) {
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setRegister(i, static_cast<uint32_t>(0x00FF00FF));
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}
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for (size_t i = 1; i < registerNum; i++) {
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buf = getRegister(i);
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if (buf != 0x00FF00FF) {
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logger->error("Register {}: 0x{:08x} != 0x{:08x}", i, buf, i);
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return false;
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}
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}
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// Reset Registers
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resetAllRegisters();
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for (size_t i = 0; i < registerNum; i++) {
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logger->debug("Register {}: 0x{:08x}", i, getRegister(i));
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}
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return true;
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}
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void AxisCache::setRegister(size_t reg, uint32_t value) {
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if (reg >= registerNum) {
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logger->error("Register index out of range: {}/{}", reg, registerNum);
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throw std::out_of_range("Register index out of range");
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}
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Xil_Out32(getBaseAddr(registerMemory) + REGISTER_OUT(reg), value);
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}
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uint32_t AxisCache::getRegister(size_t reg) {
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if (reg >= registerNum) {
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logger->error("Register index out of range: {}/{}", reg, registerNum);
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throw std::out_of_range("Register index out of range");
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}
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return Xil_In32(getBaseAddr(registerMemory) + REGISTER_OUT(reg));
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}
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void AxisCache::resetRegister(size_t reg) { setRegister(reg, 0); }
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void AxisCache::resetAllRegisters() {
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for (size_t i = 1; i < registerNum; i++) {
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resetRegister(i);
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}
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}
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AxisCache::~AxisCache() {}
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static char n[] = "axis_cache";
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static char d[] = "Register interface VHDL module 'axi_read_cache'";
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static char v[] = "xilinx.com:module_ref:axi_read_cache:";
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static CorePlugin<AxisCache, n, d, v> f;
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