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https://git.rwth-aachen.de/acs/public/villas/node/
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Add intial header file for Aurora
This commit is contained in:
Hatim Kanchwala
parent
dd1a17c4a5
commit
73e85f2e5a
2 changed files with 400 additions and 0 deletions
317
fpga/etc/vc707_villas.json
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317
fpga/etc/vc707_villas.json
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{
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"affinity": 1,
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"stats": 3,
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"name": "villas-acs",
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"logging": {
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"level": 5,
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"faciltities": [
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"path",
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"socket"
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],
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"file": "/var/log/villas-node.log",
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"syslog": true
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},
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"http": {
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"enabled": true,
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"htdocs": "/villas/web/socket/",
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"port": 80
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},
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"plugins": [
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"simple_circuit.so",
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"example_hook.so"
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],
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"fpgas": {
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"vc707": {
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"id": "10ee:7022",
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"do_reset": true,
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"ips":
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{
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"hier_0_aurora_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:user:aurora:1.9",
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S00_AXIS",
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"name": "m_axis"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M00_AXIS",
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"name": "s_axis"
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}
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]
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},
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"pcie_0_axi_reset_0": {
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"vlnv": "xilinx.com:ip:axi_gpio:2.0"
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},
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"hier_0_axis_data_fifo_1": {
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"vlnv": "xilinx.com:ip:axis_data_fifo:2.0",
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S04_AXIS",
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"name": "AXIS"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M04_AXIS",
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"name": "AXIS"
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}
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]
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},
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"hier_0_axi_dma_axi_dma_0": {
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"vlnv": "xilinx.com:ip:axi_dma:7.1",
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S01_AXIS",
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"name": "MM2S"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M01_AXIS",
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"name": "S2MM"
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}
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],
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"memory-view": {
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"M_AXI_MM2S": {
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"pcie_0_axi_pcie_0": {
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"BAR0": {
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"highaddr": 4294967295,
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"baseaddr": 0,
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"size": 4294967296
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}
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}
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},
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"M_AXI_S2MM": {
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"pcie_0_axi_pcie_0": {
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"BAR0": {
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"highaddr": 4294967295,
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"baseaddr": 0,
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"size": 4294967296
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}
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}
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}
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},
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"irqs": {
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"mm2s_introut": "pcie_0_axi_pcie_intc_0:2",
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"s2mm_introut": "pcie_0_axi_pcie_intc_0:3"
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}
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},
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"timer_0_axi_timer_0": {
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"vlnv": "xilinx.com:ip:axi_timer:2.0",
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"irqs": {
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"generateout0": "pcie_0_axi_pcie_intc_0:0"
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}
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},
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"pcie_0_axi_pcie_0": {
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"pcie_bars": {
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"BAR0": {
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"translation": 0
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}
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},
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"axi_bars": {
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"BAR0": {
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"highaddr": 4294967295,
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"translation": 0,
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"baseaddr": 0,
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"size": 4294967296
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}
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},
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"vlnv": "xilinx.com:ip:axi_pcie:2.9",
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"memory-view": {
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"M_AXI": {
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"hier_0_aurora_0": {
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"reg0": {
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"highaddr": 28671,
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"baseaddr": 24576,
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"size": 4096
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}
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},
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"pcie_0_axi_pcie_0": {
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"CTL0": {
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"highaddr": 536870911,
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"baseaddr": 268435456,
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"size": 268435456
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}
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},
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"hier_0_axi_dma_axi_dma_0": {
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"Reg": {
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"highaddr": 16383,
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"baseaddr": 12288,
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"size": 4096
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}
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},
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"pcie_0_axi_pcie_intc_0": {
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"reg0": {
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"highaddr": 8191,
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"baseaddr": 4096,
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"size": 4096
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}
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},
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"timer_0_axi_timer_0": {
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"Reg": {
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"highaddr": 20479,
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"baseaddr": 16384,
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"size": 4096
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}
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},
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"hier_0_axi_fifo_mm_s_0": {
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"Mem1": {
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"highaddr": 57343,
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"baseaddr": 49152,
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"size": 8192
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},
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"Mem0": {
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"highaddr": 40959,
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"baseaddr": 32768,
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"size": 8192
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}
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},
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"pcie_0_axi_reset_0": {
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"Reg": {
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"highaddr": 32767,
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"baseaddr": 28672,
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"size": 4096
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}
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},
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"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
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"Reg": {
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"highaddr": 24575,
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"baseaddr": 20480,
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"size": 4096
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}
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}
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}
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}
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},
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"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
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"num_ports": 5,
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"vlnv": "xilinx.com:ip:axis_switch:1.1",
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"ports": [
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{
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"role": "slave",
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"target": "hier_0_aurora_0:m_axis",
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"name": "S00_AXIS"
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},
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{
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"role": "master",
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"target": "hier_0_aurora_0:s_axis",
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"name": "M00_AXIS"
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},
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{
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"role": "slave",
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"target": "hier_0_axi_dma_axi_dma_0:MM2S",
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"name": "S01_AXIS"
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},
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{
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"role": "master",
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"target": "hier_0_axi_dma_axi_dma_0:S2MM",
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"name": "M01_AXIS"
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},
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{
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"role": "slave",
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"target": "hier_0_axi_fifo_mm_s_0:STR_TXD",
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"name": "S02_AXIS"
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},
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{
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"role": "master",
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"target": "hier_0_axi_fifo_mm_s_0:STR_RXD",
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"name": "M02_AXIS"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_data_fifo_0:AXIS",
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"name": "S03_AXIS"
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},
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{
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"role": "master",
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"target": "hier_0_axis_data_fifo_0:AXIS",
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"name": "M03_AXIS"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_data_fifo_1:AXIS",
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"name": "S04_AXIS"
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},
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{
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"role": "master",
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"target": "hier_0_axis_data_fifo_1:AXIS",
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"name": "M04_AXIS"
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}
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]
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},
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"hier_0_axis_data_fifo_0": {
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"vlnv": "xilinx.com:ip:axis_data_fifo:2.0",
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S03_AXIS",
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"name": "AXIS"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M03_AXIS",
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"name": "AXIS"
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}
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]
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},
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"pcie_0_axi_pcie_intc_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.3"
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},
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"hier_0_axi_fifo_mm_s_0": {
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"vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.2",
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S02_AXIS",
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"name": "STR_TXD"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M02_AXIS",
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"name": "STR_RXD"
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}
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],
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"irqs": {
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"interrupt": "pcie_0_axi_pcie_intc_0:1"
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}
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}
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}
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}
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},
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"nodes": {
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"dma_0": {
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"type": "fpga",
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"datamover": "dma_0",
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"use_irqs": false
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},
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"dma_1": {
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"type": "fpga",
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"datamover": "dma_1",
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"use_irqs": false
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},
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"fifo_0": {
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"type": "fpga",
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"datamover": "fifo_mm_s_0",
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"use_irqs": false
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},
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"simple_circuit": {
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"type": "cbuilder",
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"model": "simple_circuit",
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"timestep": 2.5000000000000001e-5,
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"parameters": [
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1.0,
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0.001
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]
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}
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},
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"paths": [
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{
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"in": "dma_1",
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"out": "simple_circuit",
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"reverse": true
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}
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]
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}
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83
fpga/include/villas/fpga/ips/aurora.hpp
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83
fpga/include/villas/fpga/ips/aurora.hpp
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/** Driver for wrapper around Aurora (acs.eonerc.rwth-aachen.de:user:aurora)
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*
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* @file
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* @author Hatim Kanchwala <hatim@hatimak.me>
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* @copyright 2020, Hatim Kanchwala
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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/** @addtogroup fpga VILLASfpga
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* @{
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*/
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#pragma once
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#include <villas/fpga/ip_node.hpp>
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namespace villas {
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namespace fpga {
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namespace ip {
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class Aurora : public IpNode {
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public:
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static constexpr const char* masterPort = "m_axis";
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static constexpr const char* slavePort = "s_axis";
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void dump();
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double getDt();
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std::list<std::string> getMemoryBlocks() const
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{ return { registerMemory }; }
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const StreamVertex&
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getDefaultSlavePort() const
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{ return getSlavePort(slavePort); }
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const StreamVertex&
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getDefaultMasterPort() const
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{ return getMasterPort(masterPort); }
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private:
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static constexpr const char registerMemory[] = "reg0";
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};
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class AuroraFactory : public IpNodeFactory {
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public:
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AuroraFactory();
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IpCore* create()
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{ return new Aurora; }
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std::string
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getName() const
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{ return "Aurora"; }
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std::string
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getDescription() const
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{ return "Aurora 8B/10B and additional support modules, like, communication with NovaCor and read/write status/control registers."; }
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Vlnv getCompatibleVlnv() const
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{ return {"acs.eonerc.rwth-aachen.de:user:aurora:"}; }
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};
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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/** @} */
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