refactor: more code-style improvements

fpga/gpu/src/gpu.cpp

@@ -115,14 +115,14 @@ bool Gpu::registerIoMemory(const MemoryBlock &mem)
 		// overlapping window, so this will fail badly!
 		auto translation = mm.getTranslation(masterPciEAddrSpaceId,
 		                                     mem.getAddrSpaceId());
-		if (translation.getSize() >= mem.getSize()) {
+		if (translation.getSize() >= mem.getSize())
 			// there is already a sufficient path
 			logger->debug("Already mapped through another mapping");
 			return true;
-		} else {
+		else 
 			logger->warn("There's already a mapping, but too small");
-		}
-	} catch(const std::out_of_range&) {
+	}
+	catch(const std::out_of_range&) {
 		// not yet reachable, that's okay, proceed
 	}
 
@@ -333,7 +333,8 @@ Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock &mem)
 		              mem.getAddrSpaceId());
 
 		return registerIoMemory(mem);
-	} else {
+	}
+	else {
 		logger->debug("Memory block {} is assumed to be non-CUDA host memory",
 		              mem.getAddrSpaceId());
 
@@ -400,8 +401,8 @@ GpuAllocator::allocateBlock(size_t size)
 		logger->debug("Found existing chunk that can host the requested block");
 
 		return (*chunk)->allocateBlock(size);
-
-	} else {
+	}
+	else {
 		// allocate a new chunk
 
 		// rounded-up multiple of GPU page size

fpga/include/villas/fpga/card.hpp

@@ -75,9 +75,15 @@ public:
 	bool reset() { return true; }
 	void dump()  { }
 
-	ip::Core::Ptr lookupIp(const std::string &name) const;
-	ip::Core::Ptr lookupIp(const Vlnv &vlnv) const;
-	ip::Core::Ptr lookupIp(const ip::IpIdentifier &id) const;
+	ip::Core::Ptr
+	lookupIp(const std::string &name) const;
+	
+	ip::Core::Ptr
+	lookupIp(const Vlnv &vlnv) const;
+	
+	ip::Core::Ptr
+	lookupIp(const ip::IpIdentifier &id) const;
+
 
 	bool
 	mapMemoryBlock(const MemoryBlock &block);

fpga/include/villas/fpga/node.hpp

@@ -125,8 +125,8 @@ public:
 
 protected:
 	virtual bool
-	connectInternal(const std::string& slavePort,
-	                const std::string& masterPort);
+	connectInternal(const std::string &slavePort,
+	                const std::string &masterPort);
 
 private:
 	std::pair<std::string, std::string> getLoopbackPorts() const;
@@ -142,7 +142,7 @@ class NodeFactory : public CoreFactory {
 public:
 	using CoreFactory::CoreFactory;
 
-	virtual bool configureJson(Core& ip, json_t *json_ip);
+	virtual bool configureJson(Core &ip, json_t *json_ip);
 };
 
 /** @} */

fpga/lib/core.cpp

@@ -36,7 +36,7 @@
 #include <villas/fpga/ips/intc.hpp>
 #include <villas/fpga/ips/switch.hpp>
 
-
+using namespace villas::fpga;
 using namespace villas::fpga::ip;
 
 // Special IPs that have to be initialized first. Will be initialized in the
@@ -115,10 +115,9 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
 		if (CoreFactory == nullptr) {
 			loggerStatic->warn("No plugin found to handle {}", id.getVlnv());
 			continue;
-		} else {
-			loggerStatic->debug("Using {} for IP {}",
-			                    CoreFactory->getName(), id.getVlnv());
 		}
+		else
+			loggerStatic->debug("Using {} for IP {}", CoreFactory->getName(), id.getVlnv());
 
 		auto logger = CoreFactory->getLogger();
 

fpga/lib/ips/dma.cpp

@@ -73,9 +73,9 @@ Dma::init()
 	if (XAxiDma_Selftest(&xDma) != XST_SUCCESS) {
 		logger->error("DMA selftest failed");
 		return false;
-	} else {
-		logger->debug("DMA selftest passed");
 	}
+	else
+		logger->debug("DMA selftest passed");
 
 	/* Map buffer descriptors */
 	if (hasScatterGather()) {

fpga/lib/ips/pcie.cpp

@@ -157,12 +157,10 @@ AxiPciExpressBridgeFactory::configureJson(Core &ip, json_t* json_ip)
 				    .size = static_cast<size_t>(size),
 				    .translation = translation
 				};
-
-			} else {
+			} else
 				pcie.pcieToAxiTranslations[bar_name] = {
 				    .translation = translation
 				};
-			}
 		}
 	}