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fpga: improve comments and removed dead code

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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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Niklas Eiling 2024-05-28 09:34:14 +02:00 • committed by pipeacosta
parent 4017441bf3
commit 8320e4f7c3
2 changed files with 9 additions and 7 deletions
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13
include/villas/nodes/fpga.hpp
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@ -47,11 +47,14 @@ protected:
// This sets the requested timestep in the FPGA timestep generation IP.
// The value is interpreted as seconds (i.e. 10e-3 is a timestep of 10ms).
// It is used to program the Register IP that in turn generates conversions
// of DinoAdc. This means that this setting represents the inverse of the
// Dino sampling rate.
// The setting must be programmed using DinoAdc::setRegisterConfigTimestep,
// which FpgaNode does in prepare only if a Register and a DinoAdc is present.
// This does not generate a clock, but a pulse at a configurable interval
// that is (mostly) independent from the actual clock. If the FPGA is
// coupled with a simulation, this should be the actual time step, i.e.,
// we generate the time step signal in FPGA and synchronize our simulator
// software to that signal.
// This setting is also the inverse of the Dino sampling rate if one is connected.
// For this, the setting must be programmed using DinoAdc::setRegisterConfigTimestep,
// which FpgaNode does in prepare, but only if a Register and a DinoAdc is present.
double timestep;
// State

3
lib/nodes/fpga.cpp
View file

@ -74,8 +74,7 @@ int FpgaNode::prepare() {
if (reg != nullptr &&
card->lookupIp(fpga::Vlnv("xilinx.com:module_ref:dinoif_fast:"))) {
// constexpr double sampleRate = 20e3; // We want to achieve a timestep of 50us
fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, 10e-3);
fpga::ip::DinoAdc::setRegisterConfigTimestep(reg, 10e-3);
} else {
logger->warn("No DinoAdc or no Register found on FPGA.");
}