Merge pull request #81 from VILLASframework/dma-ingress

adds C bindings and other smaller changes

fpga/etc/fpgas.json

@@ -4,7 +4,7 @@
         "id": "10ee:7021",
         "slot": "0000:88:00.0",
         "do_reset": true,
-        "ips": "etc/vc707-xbar-pcie/vc707-xbar-pcie.json",
+        "ips": "vc707-xbar-pcie/vc707-xbar-pcie.json",
         "polling": false
       }
     }

fpga/include/villas/fpga/dma.h

@@ -0,0 +1,39 @@
+/** C bindings for VILLASfpga
+ *
+ * Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
+ * SPDX-FileCopyrightText: 2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
+ * SPDX-License-Identifier: Apache-2.0
+ ******************************************************************************/
+
+#ifndef _VILLASFPGA_DMA_H
+#define _VILLASFPGA_DMA_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include <stddef.h>
+
+typedef struct villasfpga_handle_t *villasfpga_handle;
+typedef struct villasfpga_memory_t *villasfpga_memory;
+
+villasfpga_handle villasfpga_init(const char *configFile);
+
+void villasfpga_destroy(villasfpga_handle handle);
+
+int villasfpga_alloc(villasfpga_handle handle, villasfpga_memory *mem, size_t size);
+int villasfpga_register(villasfpga_handle handle, villasfpga_memory *mem);
+int villasfpga_free(villasfpga_memory mem);
+void* villasfpga_get_ptr(villasfpga_memory mem);
+
+int villasfpga_read(villasfpga_handle handle, villasfpga_memory mem, size_t size);
+int villasfpga_read_complete(villasfpga_handle handle, size_t *size);
+
+int villasfpga_write(villasfpga_handle handle, villasfpga_memory mem, size_t size);
+int villasfpga_write_complete(villasfpga_handle handle, size_t *size);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif /* _VILLASFPGA_DMA_H */

fpga/include/villas/fpga/ips/dma.hpp

@@ -129,7 +129,7 @@ private:
 	int delay = 0;
 	// Coalesce is the number of messages/BDs to wait for before issuing an interrupt
 	uint32_t writeCoalesce = 1;
-	uint32_t readCoalesce = 16;
+	uint32_t readCoalesce = 1;
 
 	// (maximum) size of a single message on the read channel in bytes.
 	// The message buffer/BD should have enough room for this many bytes.

fpga/include/villas/fpga/pcie_card.hpp

@@ -14,6 +14,7 @@
 #include <set>
 #include <string>
 #include <jansson.h>
+#include <filesystem>
 
 #include <villas/plugin.hpp>
 #include <villas/memory.hpp>
@@ -78,8 +79,10 @@ protected:
 class PCIeCardFactory : public plugin::Plugin {
 public:
 
-	static
-	std::list<std::shared_ptr<PCIeCard>> make(json_t *json, std::shared_ptr<kernel::pci::DeviceList> pci, std::shared_ptr<kernel::vfio::Container> vc);
+	static std::list<std::shared_ptr<PCIeCard>> make(json_t *json,
+		std::shared_ptr<kernel::pci::DeviceList> pci,
+		std::shared_ptr<kernel::vfio::Container> vc,
+		const std::filesystem::path& searchPath = std::filesystem::path());
 
 	static
 	PCIeCard* make()

fpga/include/villas/fpga/utils.hpp

@@ -8,6 +8,7 @@
 
 #include <string>
 #include <villas/fpga/pcie_card.hpp>
+#include <villas/fpga/ips/aurora_xilinx.hpp>
 
 namespace villas {
 namespace fpga {
@@ -25,7 +26,7 @@ public:
 	int portStringToInt(std::string &str) const;
 
 	void configCrossBar(std::shared_ptr<villas::fpga::ip::Dma> dma,
-		std::vector<std::shared_ptr<fpga::ip::AuroraXilinx>>& aurora_channels) const;
+		std::vector<std::shared_ptr<villas::fpga::ip::AuroraXilinx>>& aurora_channels) const;
 
 	bool isBidirectional() const { return bidirectional; };
 	bool isDmaLoopback() const { return dmaLoopback; };
@@ -86,14 +87,16 @@ public:
 
 	virtual void format(float value) override
 	{
-		if (std::snprintf(nextBufPos(), formatStringSize+1, formatString, value) > (int)formatStringSize) {
-			throw RuntimeError("Output buffer too small");
+		size_t chars;
+		if ((chars = std::snprintf(nextBufPos(), formatStringSize+1, formatString, value)) > (int)formatStringSize) {
+			throw RuntimeError("Output buffer too small. Expected " + std::to_string(formatStringSize) +
+					   " characters, got " + std::to_string(chars));
 		}
 	}
 
 protected:
-	static constexpr char formatString[] = "%7f\n";
-	static constexpr size_t formatStringSize = 9;
+	static constexpr char formatString[] = "%013.6f\n";
+	static constexpr size_t formatStringSize = 14;
 };
 
 class BufferedSampleFormatterLong : public BufferedSampleFormatter {
@@ -111,24 +114,13 @@ public:
 	}
 
 protected:
-	static constexpr char formatString[] = "%05zd: %7f\n";
-	static constexpr size_t formatStringSize = 16;
+	static constexpr char formatString[] = "%05zd: %013.6f\n";
+	static constexpr size_t formatStringSize = 22;
 	size_t sampleCnt;
 };
 
 
-std::unique_ptr<BufferedSampleFormatter> getBufferedSampleFormatter(
-	const std::string &format,
-	size_t bufSizeInSamples)
-{
-	if (format == "long") {
-		return std::make_unique<BufferedSampleFormatterLong>(bufSizeInSamples);
-	} else if (format == "short") {
-		return std::make_unique<BufferedSampleFormatterShort>(bufSizeInSamples);
-	} else {
-		throw RuntimeError("Unknown output format '{}'", format);
-	}
-}
+std::unique_ptr<BufferedSampleFormatter> getBufferedSampleFormatter(const std::string &format, size_t bufSizeInSamples);
 
 } /* namespace fpga */
 } /* namespace villas */

fpga/lib/CMakeLists.txt

@@ -12,6 +12,7 @@ set(SOURCES
 	core.cpp
 	node.cpp
 	utils.cpp
+	dma.cpp
 
 	ips/aurora_xilinx.cpp
 	ips/aurora.cpp

fpga/lib/dma.cpp

@@ -0,0 +1,201 @@
+/** API for interacting with the FPGA DMA Controller.
+ *
+ * Author: Niklas Eiling <niklas.eiling@rwth-aachen.de>
+ * SPDX-FileCopyrightText: 2023 Niklas Eiling <niklas.eiling@rwth-aachen.de>
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+
+#include <villas/fpga/dma.h>
+
+#include <csignal>
+#include <iostream>
+#include <string>
+#include <stdexcept>
+
+#include <villas/exceptions.hpp>
+#include <villas/log.hpp>
+#include <villas/utils.hpp>
+
+#include <villas/fpga/core.hpp>
+#include <villas/fpga/card.hpp>
+#include <villas/fpga/vlnv.hpp>
+#include <villas/fpga/ips/dma.hpp>
+#include <villas/fpga/utils.hpp>
+
+using namespace villas;
+
+static std::shared_ptr<kernel::pci::DeviceList> pciDevices;
+static auto logger = villas::logging.get("villasfpga_dma");
+
+struct villasfpga_handle_t {
+	std::shared_ptr<villas::fpga::Card> card;
+	std::shared_ptr<villas::fpga::ip::Dma> dma;
+};
+struct villasfpga_memory_t {
+	std::shared_ptr<villas::MemoryBlock> block;
+};
+
+villasfpga_handle villasfpga_init(const char *configFile)
+{
+	std::string fpgaName = "vc707";
+	std::string connectStr = "3<->pipe";
+	std::string outputFormat = "short";
+	bool dumpGraph = false;
+	bool dumpAuroraChannels = true;
+	try {
+		// Logging setup
+		logging.setLevel(spdlog::level::debug);
+		fpga::setupColorHandling();
+
+		if (configFile == nullptr || configFile[0] == '\0') {
+			logger->error("No configuration file provided/ Please use -c/--config argument");
+			return nullptr;
+		}
+
+		auto handle = new villasfpga_handle_t;
+		handle->card = fpga::setupFpgaCard(configFile, fpgaName);
+
+		std::vector<std::shared_ptr<fpga::ip::AuroraXilinx>> aurora_channels;
+		for (int i = 0; i < 4; i++) {
+			auto name = fmt::format("aurora_8b10b_ch{}", i);
+			auto id = fpga::ip::IpIdentifier("xilinx.com:ip:aurora_8b10b:", name);
+			auto aurora = std::dynamic_pointer_cast<fpga::ip::AuroraXilinx>(handle->card->lookupIp(id));
+			if (aurora == nullptr) {
+				logger->error("No Aurora interface found on FPGA");
+				return nullptr;
+			}
+
+			aurora_channels.push_back(aurora);
+		}
+
+		handle->dma = std::dynamic_pointer_cast<fpga::ip::Dma>
+					(handle->card->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_dma:")));
+		if (handle->dma == nullptr) {
+			logger->error("No DMA found on FPGA ");
+			return nullptr;
+		}
+
+		if (dumpGraph) {
+			auto &mm = MemoryManager::get();
+			mm.getGraph().dump("graph.dot");
+		}
+
+		if (dumpAuroraChannels) {
+			for (auto aurora : aurora_channels)
+				aurora->dump();
+		}
+
+		// Configure Crossbar switch
+		const fpga::ConnectString parsedConnectString(connectStr);
+		parsedConnectString.configCrossBar(handle->dma, aurora_channels);
+
+		return handle;
+	} catch (const RuntimeError &e) {
+		logger->error("Error: {}", e.what());
+		return nullptr;
+	} catch (const std::exception &e) {
+		logger->error("Error: {}", e.what());
+		return nullptr;
+	} catch (...) {
+		logger->error("Unknown error");
+		return nullptr;
+	}
+}
+
+void villasfpga_destroy(villasfpga_handle handle)
+{
+	delete handle;
+}
+
+int villasfpga_alloc(villasfpga_handle handle, villasfpga_memory *mem, size_t size)
+{
+	try {
+		auto &alloc = villas::HostRam::getAllocator();
+		*mem = new villasfpga_memory_t;
+		(*mem)->block = alloc.allocateBlock(size);
+		return villasfpga_register(handle, mem);
+	} catch (const RuntimeError &e) {
+		logger->error("Failed to allocate memory: {}", e.what());
+		return -1;
+	}
+}
+int villasfpga_register(villasfpga_handle handle, villasfpga_memory *mem)
+{
+	try {
+		handle->dma->makeAccesibleFromVA((*mem)->block);
+		return 0;
+	} catch (const RuntimeError &e) {
+		logger->error("Failed to register memory: {}", e.what());
+		return -1;
+	}
+}
+int villasfpga_free(villasfpga_memory mem)
+{
+	try {
+		delete mem;
+		return 0;
+	} catch (const RuntimeError &e) {
+		logger->error("Failed to free memory: {}", e.what());
+		return -1;
+	}
+}
+
+int villasfpga_read(villasfpga_handle handle, villasfpga_memory mem, size_t size)
+{
+	try {
+		if (!handle->dma->read(*mem->block, size)) {
+			logger->error("Failed to read from device");
+			return -1;
+		}
+		return 0;
+	} catch (const RuntimeError &e) {
+		logger->error("Failed to read memory: {}", e.what());
+		return -1;
+	}
+}
+
+int villasfpga_read_complete(villasfpga_handle handle, size_t *size)
+{
+	try {
+		auto readComp = handle->dma->readComplete();
+		logger->debug("Read {} bytes", readComp.bytes);
+		*size = readComp.bytes;
+		return 0;
+	} catch (const RuntimeError &e) {
+		logger->error("Failed to read memory: {}", e.what());
+		return -1;
+	}
+}
+
+int villasfpga_write(villasfpga_handle handle, villasfpga_memory mem, size_t size)
+{
+	try {
+		if (!handle->dma->write(*mem->block, size)) {
+			logger->error("Failed to write to device");
+			return -1;
+		}
+		return 0;
+	} catch (const RuntimeError &e) {
+		logger->error("Failed to write memory: {}", e.what());
+		return -1;
+	}
+}
+
+int villasfpga_write_complete(villasfpga_handle handle, size_t *size)
+{
+	try {
+		auto writeComp = handle->dma->writeComplete();
+		logger->debug("Wrote {} bytes", writeComp.bytes);
+		*size = writeComp.bytes;
+		return 0;
+	} catch (const RuntimeError &e) {
+		logger->error("Failed to write memory: {}", e.what());
+		return -1;
+	}
+}
+
+void* villasfpga_get_ptr(villasfpga_memory mem)
+{
+	return (void*)MemoryManager::get().getTranslationFromProcess(mem->block->getAddrSpaceId()).getLocalAddr(0);
+}
+

fpga/lib/ips/dma.cpp

@@ -243,7 +243,7 @@ bool Dma::write(const MemoryBlock &mem, size_t len)
 	if (buf == nullptr)
 		throw RuntimeError("Buffer was null");
 
-	logger->debug("Write to stream from address {:p}", buf);
+	logger->trace("Write to stream from address {:p}", buf);
 
 	return hasScatterGather() ? writeScatterGather(buf, len) : writeSimple(buf, len);
 }

fpga/lib/pcie_card.cpp

@@ -27,7 +27,10 @@ static PCIeCardFactory PCIeCardFactoryInstance;
 
 static const kernel::pci::Device defaultFilter((kernel::pci::Id(FPGA_PCI_VID_XILINX, FPGA_PCI_PID_VFPGA)));
 
-std::list<std::shared_ptr<PCIeCard>> PCIeCardFactory::make(json_t *json, std::shared_ptr<kernel::pci::DeviceList> pci, std::shared_ptr<kernel::vfio::Container> vc)
+std::list<std::shared_ptr<PCIeCard>> PCIeCardFactory::make(json_t *json,
+	std::shared_ptr<kernel::pci::DeviceList> pci,
+	std::shared_ptr<kernel::vfio::Container> vc,
+	const std::filesystem::path& searchPath)
 {
 	std::list<std::shared_ptr<PCIeCard>> cards;
 	auto logger = getStaticLogger();
@@ -87,11 +90,21 @@ std::list<std::shared_ptr<PCIeCard>> PCIeCardFactory::make(json_t *json, std::sh
 		}
 
 		// Load IPs from a separate json file
-		if (json_is_string(json_ips)) {
-			auto json_ips_fn = json_string_value(json_ips);
-			json_ips = json_load_file(json_ips_fn, 0, nullptr);
-			if (json_ips == nullptr)
-				throw ConfigError(json_ips, "node-config-fpga-ips", "Failed to load FPGA IP cores from {}", json_ips_fn);
+		if (!json_is_string(json_ips)) {
+			logger->debug("FPGA IP cores config item is not a string.");
+			throw ConfigError(json_ips, "node-config-fpga-ips", "FPGA IP cores config item is not a string.");
+		}
+		if (!searchPath.empty()) {
+			std::filesystem::path json_ips_path = searchPath / json_string_value(json_ips);
+			logger->debug("searching for FPGA IP cors config at {}", json_ips_path);
+			json_ips = json_load_file(json_ips_path.c_str(), 0, nullptr);
+		}
+		if (json_ips == nullptr) {
+			json_ips = json_load_file(json_string_value(json_ips), 0, nullptr);
+			logger->debug("searching for FPGA IP cors config at {}", json_string_value(json_ips));
+			if (json_ips == nullptr) {
+				throw ConfigError(json_ips, "node-config-fpga-ips", "Failed to find FPGA IP cores config");
+			}
 		}
 
 		if (not json_is_object(json_ips))

fpga/lib/utils.cpp

@@ -13,6 +13,7 @@
 #include <algorithm>
 #include <jansson.h>
 #include <regex>
+#include <filesystem>
 
 #include <CLI11.hpp>
 #include <rang.hpp>
@@ -63,7 +64,7 @@ void fpga::ConnectString::parseString(std::string& connectString)
 		return;
 	}
 
-	static const std::regex regex("([0-9]+)([<\\->]+)([0-9]+|stdin|stdout)");
+	static const std::regex regex("([0-9]+)([<\\->]+)([0-9]+|stdin|stdout|pipe)");
 	std::smatch match;
 
 	if (!std::regex_match(connectString, match, regex) || match.size() != 4) {
@@ -84,15 +85,17 @@ void fpga::ConnectString::parseString(std::string& connectString)
 	dstAsInt = portStringToInt(dstStr);
 	if (srcAsInt == -1) {
 		srcIsStdin = true;
+		dstIsStdout = bidirectional;
 	}
 	if (dstAsInt == -1) {
 		dstIsStdout = true;
+		srcIsStdin = bidirectional;
 	}
 }
 
 int fpga::ConnectString::portStringToInt(std::string &str) const
 {
-	if (str == "stdin" || str == "stdout") {
+	if (str == "stdin" || str == "stdout" || str == "pipe") {
 		return -1;
 	} else {
 		const int port = std::stoi(str);
@@ -166,6 +169,7 @@ fpga::setupFpgaCard(const std::string &configFile, const std::string &fpgaName)
 	pciDevices = std::make_shared<kernel::pci::DeviceList>();
 
 	auto vfioContainer = std::make_shared<kernel::vfio::Container>();
+	auto configDir = std::filesystem::path(configFile).parent_path();
 
 	// Parse FPGA configuration
 	FILE* f = fopen(configFile.c_str(), "r");
@@ -195,7 +199,7 @@ fpga::setupFpgaCard(const std::string &configFile, const std::string &fpgaName)
 	}
 
 	// Create all FPGA card instances using the corresponding plugin
-	auto cards = fpgaCardFactory->make(fpgas, pciDevices, vfioContainer);
+	auto cards = fpgaCardFactory->make(fpgas, pciDevices, vfioContainer, configDir);
 
 	std::shared_ptr<fpga::PCIeCard> card;
 	for (auto &fpgaCard : cards) {
@@ -213,3 +217,15 @@ fpga::setupFpgaCard(const std::string &configFile, const std::string &fpgaName)
 	return card;
 }
 
+std::unique_ptr<fpga::BufferedSampleFormatter> fpga::getBufferedSampleFormatter(
+	const std::string &format,
+	size_t bufSizeInSamples)
+{
+	if (format == "long") {
+		return std::make_unique<fpga::BufferedSampleFormatterLong>(bufSizeInSamples);
+	} else if (format == "short") {
+		return std::make_unique<fpga::BufferedSampleFormatterShort>(bufSizeInSamples);
+	} else {
+		throw RuntimeError("Unknown output format '{}'", format);
+	}
+}

fpga/src/CMakeLists.txt

@@ -11,4 +11,11 @@ target_link_libraries(villas-fpga-ctrl PUBLIC
 	villas-fpga
 )
 
+add_executable(villas-fpga-pipe villas-fpga-pipe.cpp)
+
+target_link_libraries(villas-fpga-pipe PUBLIC
+	villas-fpga
+)
+
+
 add_executable(pcimem pcimem.c)

fpga/src/villas-fpga-ctrl.cpp

@@ -21,7 +21,6 @@
 #include <villas/exceptions.hpp>
 #include <villas/log.hpp>
 #include <villas/utils.hpp>
-#include <villas/utils.hpp>
 
 #include <villas/fpga/core.hpp>
 #include <villas/fpga/card.hpp>
@@ -39,25 +38,15 @@ static auto logger = villas::logging.get("ctrl");
 void writeToDmaFromStdIn(std::shared_ptr<villas::fpga::ip::Dma> dma)
 {
 	auto &alloc = villas::HostRam::getAllocator();
+	const std::shared_ptr<villas::MemoryBlock> block = alloc.allocateBlock(0x200 * sizeof(float));
+	villas::MemoryAccessor<float> mem = *block;
+	dma->makeAccesibleFromVA(block);
 
-	const std::shared_ptr<villas::MemoryBlock> block[] = {
-		alloc.allocateBlock(0x200 * sizeof(uint32_t)),
-		alloc.allocateBlock(0x200 * sizeof(uint32_t))
-	};
-	villas::MemoryAccessor<int32_t> mem[] = {*block[0], *block[1]};
+	logger->info("Please enter values to write to the device, separated by ';'");
 
-	for (auto b : block) {
-		dma->makeAccesibleFromVA(b);
-	}
-
-	size_t cur = 0, next = 1;
-	std::ios::sync_with_stdio(false);
-	std::string line;
-	bool firstXfer = true;
-
-	while(true) {
+	while (true) {
 		// Read values from stdin
-
+		std::string line;
 		std::getline(std::cin, line);
 		auto values = villas::utils::tokenize(line, ";");
 
@@ -66,24 +55,63 @@ void writeToDmaFromStdIn(std::shared_ptr<villas::fpga::ip::Dma> dma)
 			if (value.empty()) continue;
 
 			const float number = std::stof(value);
-			mem[cur][i++] = number;
+			mem[i++] = number;
 		}
 
 		// Initiate write transfer
-		bool state = dma->write(*block[cur], i * sizeof(float));
+		bool state = dma->write(*block, i * sizeof(float));
 		if (!state)
 			logger->error("Failed to write to device");
 
-		if (!firstXfer) {
-			auto bytesWritten = dma->writeComplete();
-			logger->debug("Wrote {} bytes", bytesWritten.bytes);
-		} else {
-			firstXfer = false;
-		}
-
-		cur = next;
-		next = (next + 1) % (sizeof(mem) / sizeof(mem[0]));
+		auto writeComp = dma->writeComplete();
+		logger->debug("Wrote {} bytes", writeComp.bytes);
 	}
+	// auto &alloc = villas::HostRam::getAllocator();
+
+	// const std::shared_ptr<villas::MemoryBlock> block[] = {
+	// 	alloc.allocateBlock(0x200 * sizeof(uint32_t)),
+	// 	alloc.allocateBlock(0x200 * sizeof(uint32_t))
+	// };
+	// villas::MemoryAccessor<int32_t> mem[] = {*block[0], *block[1]};
+
+	// for (auto b : block) {
+	// 	dma->makeAccesibleFromVA(b);
+	// }
+
+	// size_t cur = 0, next = 1;
+	// std::ios::sync_with_stdio(false);
+	// std::string line;
+	// bool firstXfer = true;
+
+	// while(true) {
+	// 	// Read values from stdin
+
+	// 	std::getline(std::cin, line);
+	// 	auto values = villas::utils::tokenize(line, ";");
+
+	// 	size_t i = 0;
+	// 	for (auto &value: values) {
+	// 		if (value.empty()) continue;
+
+	// 		const float number = std::stof(value);
+	// 		mem[cur][i++] = number;
+	// 	}
+
+	// 	// Initiate write transfer
+	// 	bool state = dma->write(*block[cur], i * sizeof(float));
+	// 	if (!state)
+	// 		logger->error("Failed to write to device");
+
+	// 	if (!firstXfer) {
+	// 		auto bytesWritten = dma->writeComplete();
+	// 		logger->debug("Wrote {} bytes", bytesWritten.bytes);
+	// 	} else {
+	// 		firstXfer = false;
+	// 	}
+
+	// 	cur = next;
+	// 	next = (next + 1) % (sizeof(mem) / sizeof(mem[0]));
+	// }
 }
 
 void readFromDmaToStdOut(std::shared_ptr<villas::fpga::ip::Dma> dma,
@@ -117,15 +145,19 @@ void readFromDmaToStdOut(std::shared_ptr<villas::fpga::ip::Dma> dma,
 			logger->warn("Missed {} interrupts", c.interrupts - 1);
 		}
 
-		logger->trace("bytes: {}, intrs: {}, bds: {}",
+		logger->debug("bytes: {}, intrs: {}, bds: {}",
 			c.bytes, c.interrupts, c.bds);
-
-		for (size_t i = 0; i*4 < c.bytes; i++) {
-			int32_t ival = mem[cur][i];
-			float fval = *((float*)(&ival)); // cppcheck-suppress invalidPointerCast
-			formatter->format(fval);
+		try {
+			for (size_t  i = 0; i*4 < c.bytes; i++) {
+				int32_t ival = mem[cur][i];
+				float fval = *((float*)(&ival)); // cppcheck-suppress invalidPointerCast
+				formatter->format(fval);
+				printf("%#x\n", ival);
+			}
+			formatter->output(std::cout);
+		} catch (const std::exception &e) {
+			logger->warn("Failed to output data: {}", e.what());
 		}
-		formatter->output(std::cout);
 
 		cur = next;
 		next = (next + 1) % (sizeof(mem) / sizeof(mem[0]));

fpga/src/villas-fpga-pipe.cpp

@@ -83,23 +83,27 @@ int main(int argc, char* argv[])
 
 		// Configure Crossbar switch
 #if 1
-		aurora_channels[2]->connect(aurora_channels[2]->getDefaultMasterPort(), dma->getDefaultSlavePort());
+		aurora_channels[3]->connect(aurora_channels[3]->getDefaultMasterPort(), dma->getDefaultSlavePort());
 		dma->connect(dma->getDefaultMasterPort(), aurora_channels[3]->getDefaultSlavePort());
 #else
 		dma->connectLoopback();
 #endif
 		auto &alloc = villas::HostRam::getAllocator();
-		auto mem = alloc.allocate<int32_t>(0x100);
-		auto block = mem.getMemoryBlock();
-
-		dma->makeAccesibleFromVA(block);
+		const std::shared_ptr<villas::MemoryBlock> block[] = {
+			alloc.allocateBlock(0x200 * sizeof(uint32_t)),
+			alloc.allocateBlock(0x200 * sizeof(uint32_t))
+		};
+		villas::MemoryAccessor<int32_t> mem[] = {*block[0], *block[1]};
 
+		for (auto b : block) {
+			dma->makeAccesibleFromVA(b);
+		}
 		auto &mm = MemoryManager::get();
 		mm.getGraph().dump("graph.dot");
 
 		while (true) {
 			// Setup read transfer
-			dma->read(block, block.getSize());
+			dma->read(*block[0], block[0]->getSize());
 
 			// Read values from stdin
 			std::string line;
@@ -111,23 +115,23 @@ int main(int argc, char* argv[])
 				if (value.empty()) continue;
 
 				const int32_t number = std::stoi(value);
-				mem[i++] = number;
+				mem[1][i++] = number;
 			}
 
 			// Initiate write transfer
-			bool state = dma->write(block, i * sizeof(int32_t));
+			bool state = dma->write(*block[1], i * sizeof(int32_t));
 			if (!state)
 				logger->error("Failed to write to device");
 
-			auto bytesWritten = dma->writeComplete();
-			logger->info("Wrote {} bytes", bytesWritten);
+			auto writeComp = dma->writeComplete();
+			logger->info("Wrote {} bytes", writeComp.bytes);
 
-			auto bytesRead = dma->readComplete();
-			auto valuesRead = bytesRead / sizeof(int32_t);
-			logger->info("Read {} bytes", bytesRead);
+			auto readComp = dma->readComplete();
+			auto valuesRead = readComp.bytes / sizeof(int32_t);
+			logger->info("Read {} bytes, {} bds, {} interrupts", readComp.bytes, readComp.bds, readComp.interrupts);
 
 			for (size_t i = 0; i < valuesRead; i++)
-				std::cerr << mem[i] << ";";
+				std::cerr << mem[0][i] << ";";
 			std::cerr << std::endl;
 		}
 	} catch (const RuntimeError &e) {

fpga/tests/unit/CMakeLists.txt

@@ -36,3 +36,13 @@ target_link_libraries(unit-tests-fpga PUBLIC
 	villas-fpga
 	${CRITERION_LIBRARIES}
 )
+
+add_executable(villasfpga-dma dma.c)
+
+target_include_directories(villasfpga-dma PUBLIC
+	../include
+)
+
+target_link_libraries(villasfpga-dma PUBLIC
+	villas-fpga
+)

fpga/tests/unit/dma.c

@@ -0,0 +1,103 @@
+/** Testing the C bindings for the VILLASfpga DMA interface.
+ *
+ * Author: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
+ * SPDX-FileCopyrightText: 2023 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+
+#include <villas/fpga/dma.h>
+
+int main(int argc, char *argv[])
+{
+	int ret;
+	villasfpga_handle vh;
+	villasfpga_memory mem1, mem2;
+	void *mem1ptr, *mem2ptr;
+	char line[1024];
+	float f;
+	size_t size;
+
+	if (argv == NULL) {
+		return 1;
+	}
+	if (argc != 2 || argv[1] == NULL) {
+		fprintf(stderr, "Usage: %s <config file>\n", argv[0]);
+	}
+
+	if ((vh = villasfpga_init(argv[1])) == NULL) {
+		fprintf(stderr, "Failed to initialize FPGA\n");
+		ret = 1;
+		goto out;
+	}
+
+	if (villasfpga_alloc(vh, &mem1, 0x200 * sizeof(uint32_t)) != 0) {
+		fprintf(stderr, "Failed to allocate DMA memory 1\n");
+		ret = 1;
+		goto out;
+	}
+
+	if (villasfpga_alloc(vh, &mem2, 0x200 * sizeof(uint32_t)) != 0) {
+		fprintf(stderr, "Failed to allocate DMA memory 2\n");
+		ret = 1;
+		goto out;
+	}
+
+	if ((mem1ptr = villasfpga_get_ptr(mem1)) == NULL) {
+		fprintf(stderr, "Failed to get pointer to DMA memory 1\n");
+		ret = 1;
+		goto out;
+	}
+
+	if ((mem2ptr = villasfpga_get_ptr(mem2)) == NULL) {
+		fprintf(stderr, "Failed to get pointer to DMA memory 2\n");
+		ret = 1;
+		goto out;
+	}
+
+	printf("DMA memory 1: %p, DMA memory 2: %p\n", mem1ptr, mem2ptr);
+
+	while (1) {
+		// Setup read transfer
+		if ((ret = villasfpga_read(vh, mem1, 0x200 * sizeof(uint32_t))) != 0) {
+			fprintf(stderr, "Failed to initiate read transfer\n");
+			ret = 1;
+			goto out;
+		}
+
+		printf("Enter a float:\n");
+		if ((ret = scanf("%f", (float*)mem2ptr)) != 1) {
+			fprintf(stderr, "Failed to parse input: sscanf returned %d\n", ret);
+			ret = 1;
+			goto out;
+		}
+		printf("sending %f (%zu bytes)\n", ((float*)mem2ptr)[0], sizeof(float));
+		// Initiate write transfer
+		if ((ret = villasfpga_write(vh, mem2, sizeof(float))) != 0) {
+			fprintf(stderr, "Failed to initiate write transfer\n");
+			ret = 1;
+			goto out;
+		}
+
+		if ((ret = villasfpga_write_complete(vh, &size)) != 0) {
+			fprintf(stderr, "Failed to write complete\n");
+			ret = 1;
+			goto out;
+		}
+
+		if ((ret = villasfpga_read_complete(vh, &size)) != 0) {
+			fprintf(stderr, "Failed to write complete\n");
+			ret = 1;
+			goto out;
+		}
+
+		printf("Read %f (%zu bytes)\n", ((float*)mem1ptr)[0], size);
+	}
+
+	ret = 0;
+ out:
+	return ret;
+}