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Code Issues Releases Wiki Activity

refactor: whitespaces for references

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This commit is contained in:
Steffen Vogel 2020-06-14 22:03:50 +02:00
parent e86a291dfd
commit 8b7bbe27c6
33 changed files with 175 additions and 177 deletions
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20
fpga/gpu/include/villas/gpu.hpp
View file

@ -45,25 +45,25 @@ public:
std::string getName() const;
GpuAllocator& getAllocator() const
GpuAllocator &getAllocator() const
{ return *allocator; }
bool makeAccessibleToPCIeAndVA(const MemoryBlock& mem);
bool makeAccessibleToPCIeAndVA(const MemoryBlock &mem);
/// Make some memory block accssible for this GPU
bool makeAccessibleFromPCIeOrHostRam(const MemoryBlock& mem);
bool makeAccessibleFromPCIeOrHostRam(const MemoryBlock &mem);
void memcpySync(const MemoryBlock& src, const MemoryBlock& dst, size_t size);
void memcpySync(const MemoryBlock &src, const MemoryBlock &dst, size_t size);
void memcpyKernel(const MemoryBlock& src, const MemoryBlock& dst, size_t size);
void memcpyKernel(const MemoryBlock &src, const MemoryBlock &dst, size_t size);
MemoryTranslation
translate(const MemoryBlock& dst);
translate(const MemoryBlock &dst);
private:
bool registerIoMemory(const MemoryBlock& mem);
bool registerHostMemory(const MemoryBlock& mem);
bool registerIoMemory(const MemoryBlock &mem);
bool registerHostMemory(const MemoryBlock &mem);
private:
class impl;
@ -86,7 +86,7 @@ class GpuAllocator : public BaseAllocator<GpuAllocator> {
public:
static constexpr size_t GpuPageSize = 64UL << 10;
GpuAllocator(Gpu& gpu);
GpuAllocator(Gpu &gpu);
std::string getName() const;
@ -94,7 +94,7 @@ public:
allocateBlock(size_t size);
private:
Gpu& gpu;
Gpu &gpu;
// TODO: replace by multimap (key is available memory)
std::list<std::unique_ptr<LinearAllocator>> chunks;
};

42
fpga/gpu/src/gpu.cpp
View file

@ -30,7 +30,7 @@
#include <villas/gpu.hpp>
#include <villas/log.hpp>
#include <villas/kernel/pci.h>
#include <villas/kernel/pci.hpp>
#include <villas/memory_manager.hpp>
#include <cuda.h>
@ -44,7 +44,7 @@ namespace gpu {
static GpuFactory gpuFactory;
GpuAllocator::GpuAllocator(Gpu& gpu) :
GpuAllocator::GpuAllocator(Gpu &gpu) :
BaseAllocator(gpu.masterPciEAddrSpaceId),
gpu(gpu)
{
@ -77,7 +77,7 @@ GpuFactory::GpuFactory() :
// required to be defined here for PIMPL to compile
Gpu::~Gpu()
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
mm.removeAddressSpace(masterPciEAddrSpaceId);
}
@ -104,9 +104,9 @@ std::string Gpu::getName() const
return name.str();
}
bool Gpu::registerIoMemory(const MemoryBlock& mem)
bool Gpu::registerIoMemory(const MemoryBlock &mem)
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
const auto pciAddrSpaceId = mm.getPciAddressSpace();
// Check if we need to map anything at all, maybe it's already reachable
@ -187,9 +187,9 @@ bool Gpu::registerIoMemory(const MemoryBlock& mem)
}
bool
Gpu::registerHostMemory(const MemoryBlock& mem)
Gpu::registerHostMemory(const MemoryBlock &mem)
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
auto translation = mm.getTranslationFromProcess(mem.getAddrSpaceId());
auto localBase = reinterpret_cast<void*>(translation.getLocalAddr(0));
@ -214,14 +214,14 @@ Gpu::registerHostMemory(const MemoryBlock& mem)
return true;
}
bool Gpu::makeAccessibleToPCIeAndVA(const MemoryBlock& mem)
bool Gpu::makeAccessibleToPCIeAndVA(const MemoryBlock &mem)
{
if (pImpl->gdr == nullptr) {
logger->warn("GDRcopy not available");
return false;
}
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
try {
auto path = mm.findPath(masterPciEAddrSpaceId, mem.getAddrSpaceId());
@ -311,14 +311,14 @@ bool Gpu::makeAccessibleToPCIeAndVA(const MemoryBlock& mem)
}
bool
Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock& mem)
Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock &mem)
{
// Check which kind of memory this is and where it resides
// There are two possibilities:
// - Host memory not managed by CUDA
// - IO memory somewhere on the PCIe bus
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
bool isIoMemory = false;
try {
@ -341,9 +341,9 @@ Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock& mem)
}
}
void Gpu::memcpySync(const MemoryBlock& src, const MemoryBlock& dst, size_t size)
void Gpu::memcpySync(const MemoryBlock &src, const MemoryBlock &dst, size_t size)
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
auto src_translation = mm.getTranslation(masterPciEAddrSpaceId,
src.getAddrSpaceId());
@ -357,9 +357,9 @@ void Gpu::memcpySync(const MemoryBlock& src, const MemoryBlock& dst, size_t size
cudaMemcpy(dst_buf, src_buf, size, cudaMemcpyDefault);
}
void Gpu::memcpyKernel(const MemoryBlock& src, const MemoryBlock& dst, size_t size)
void Gpu::memcpyKernel(const MemoryBlock &src, const MemoryBlock &dst, size_t size)
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
auto src_translation = mm.getTranslation(masterPciEAddrSpaceId,
src.getAddrSpaceId());
@ -375,9 +375,9 @@ void Gpu::memcpyKernel(const MemoryBlock& src, const MemoryBlock& dst, size_t si
}
MemoryTranslation
Gpu::translate(const MemoryBlock& dst)
Gpu::translate(const MemoryBlock &dst)
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
return mm.getTranslation(masterPciEAddrSpaceId, dst.getAddrSpaceId());
}
@ -388,10 +388,10 @@ GpuAllocator::allocateBlock(size_t size)
cudaSetDevice(gpu.gpuId);
void* addr;
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
// search for an existing chunk that has enough free memory
auto chunk = std::find_if(chunks.begin(), chunks.end(), [&](const auto& chunk) {
auto chunk = std::find_if(chunks.begin(), chunks.end(), [&](const auto &chunk) {
return chunk->getAvailableMemory() >= size;
});
@ -452,7 +452,7 @@ Gpu::Gpu(int gpuId) :
bool Gpu::init()
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
const auto gpuPciEAddrSpaceName = mm.getMasterAddrSpaceName(getName(), "pcie");
masterPciEAddrSpaceId = mm.getOrCreateAddressSpace(gpuPciEAddrSpaceName);
@ -517,7 +517,7 @@ GpuFactory::make()
}
logger->info("Initialized {} GPUs", gpuList.size());
for (auto& gpu : gpuList) {
for (auto &gpu : gpuList) {
logger->debug(" - {}", gpu->getName());
}

8
fpga/include/villas/fpga/card.hpp
View file

@ -75,12 +75,12 @@ public:
bool reset() { return true; }
void dump() { }
ip::Core::Ptr lookupIp(const std::string& name) const;
ip::Core::Ptr lookupIp(const Vlnv& vlnv) const;
ip::Core::Ptr lookupIp(const ip::IpIdentifier& id) const;
ip::Core::Ptr lookupIp(const std::string &name) const;
ip::Core::Ptr lookupIp(const Vlnv &vlnv) const;
ip::Core::Ptr lookupIp(const ip::IpIdentifier &id) const;
bool
mapMemoryBlock(const MemoryBlock& block);
mapMemoryBlock(const MemoryBlock &block);
private:
/// Cache a set of already mapped memory blocks

40
fpga/include/villas/fpga/core.hpp
View file

@ -74,11 +74,11 @@ public:
{ return vlnv; }
friend std::ostream&
operator<< (std::ostream& stream, const IpIdentifier& id)
operator<< (std::ostream &stream, const IpIdentifier &id)
{ return stream << id.name << " vlnv=" << id.vlnv; }
bool
operator==(const IpIdentifier& otherId) const {
operator==(const IpIdentifier &otherId) const {
const bool vlnvWildcard = otherId.getVlnv() == Vlnv::getWildcard();
const bool nameWildcard = this->getName().empty() or otherId.getName().empty();
@ -89,7 +89,7 @@ public:
}
bool
operator!=(const IpIdentifier& otherId) const
operator!=(const IpIdentifier &otherId) const
{ return !(*this == otherId); }
private:
@ -144,66 +144,66 @@ public:
/* Operators */
bool
operator==(const Vlnv& otherVlnv) const
operator==(const Vlnv &otherVlnv) const
{ return id.getVlnv() == otherVlnv; }
bool
operator!=(const Vlnv& otherVlnv) const
operator!=(const Vlnv &otherVlnv) const
{ return id.getVlnv() != otherVlnv; }
bool
operator==(const IpIdentifier& otherId) const
operator==(const IpIdentifier &otherId) const
{ return this->id == otherId; }
bool
operator!=(const IpIdentifier& otherId) const
operator!=(const IpIdentifier &otherId) const
{ return this->id != otherId; }
bool
operator==(const std::string& otherName) const
operator==(const std::string &otherName) const
{ return getInstanceName() == otherName; }
bool
operator!=(const std::string& otherName) const
operator!=(const std::string &otherName) const
{ return getInstanceName() != otherName; }
bool
operator==(const Core& otherIp) const
operator==(const Core &otherIp) const
{ return this->id == otherIp.id; }
bool
operator!=(const Core& otherIp) const
operator!=(const Core &otherIp) const
{ return this->id != otherIp.id; }
friend std::ostream&
operator<< (std::ostream& stream, const Core& ip)
operator<< (std::ostream &stream, const Core &ip)
{ return stream << ip.id; }
protected:
uintptr_t
getBaseAddr(const MemoryBlockName& block) const
getBaseAddr(const MemoryBlockName &block) const
{ return getLocalAddr(block, 0); }
uintptr_t
getLocalAddr(const MemoryBlockName& block, uintptr_t address) const;
getLocalAddr(const MemoryBlockName &block, uintptr_t address) const;
MemoryManager::AddressSpaceId
getAddressSpaceId(const MemoryBlockName& block) const
getAddressSpaceId(const MemoryBlockName &block) const
{ return slaveAddressSpaces.at(block); }
InterruptController*
getInterruptController(const std::string& interruptName) const;
getInterruptController(const std::string &interruptName) const;
MemoryManager::AddressSpaceId
getMasterAddrSpaceByInterface(const std::string& masterInterfaceName) const
getMasterAddrSpaceByInterface(const std::string &masterInterfaceName) const
{ return busMasterInterfaces.at(masterInterfaceName); }
template<typename T>
T readMemory(const std::string& block, uintptr_t address) const
T readMemory(const std::string &block, uintptr_t address) const
{ return *(reinterpret_cast<T*>(getLocalAddr(block, address))); }
template<typename T>
void writeMemory(const std::string& block, uintptr_t address, T value)
void writeMemory(const std::string &block, uintptr_t address, T value)
{ T* ptr = reinterpret_cast<T*>(getLocalAddr(block, address)); *ptr = value; }
protected:
@ -266,7 +266,7 @@ protected:
private:
static CoreFactory*
lookup(const Vlnv& vlnv);
lookup(const Vlnv &vlnv);
};
/** @} */

2
fpga/include/villas/fpga/ips/bram.hpp
View file

@ -59,7 +59,7 @@ private:
class BramFactory : public CoreFactory {
public:
bool configureJson(Core& ip, json_t *json_ip);
bool configureJson(Core &ip, json_t *json_ip);
Core* create()
{ return new Bram; }

12
fpga/include/villas/fpga/ips/dma.hpp
View file

@ -44,10 +44,10 @@ public:
bool reset();
// memory-mapped to stream (MM2S)
bool write(const MemoryBlock& mem, size_t len);
bool write(const MemoryBlock &mem, size_t len);
// stream to memory-mapped (S2MM)
bool read(const MemoryBlock& mem, size_t len);
bool read(const MemoryBlock &mem, size_t len);
size_t writeComplete()
{ return hasScatterGather() ? writeCompleteSG() : writeCompleteSimple(); }
@ -55,10 +55,10 @@ public:
size_t readComplete()
{ return hasScatterGather() ? readCompleteSG() : readCompleteSimple(); }
bool memcpy(const MemoryBlock& src, const MemoryBlock& dst, size_t len);
bool memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len);
bool makeAccesibleFromVA(const MemoryBlock& mem);
bool makeInaccesibleFromVA(const MemoryBlock& mem);
bool makeAccesibleFromVA(const MemoryBlock &mem);
bool makeInaccesibleFromVA(const MemoryBlock &mem);
inline bool
hasScatterGather() const
@ -87,7 +87,7 @@ public:
static constexpr const char* s2mmPort = "S2MM";
static constexpr const char* mm2sPort = "MM2S";
bool isMemoryBlockAccesible(const MemoryBlock& mem, const std::string& interface);
bool isMemoryBlockAccesible(const MemoryBlock &mem, const std::string &interface);
virtual void dump();

2
fpga/include/villas/fpga/ips/hls.hpp
View file

@ -13,7 +13,7 @@ class Hls : public virtual Core
public:
virtual bool init()
{
auto& registers = addressTranslations.at(registerMemory);
auto &registers = addressTranslations.at(registerMemory);
controlRegister = reinterpret_cast<ControlRegister*>(registers.getLocalAddr(registerControlAddr));
globalIntRegister = reinterpret_cast<GlobalIntRegister*>(registers.getLocalAddr(registerGlobalIntEnableAddr));

2
fpga/include/villas/fpga/ips/pcie.hpp
View file

@ -70,7 +70,7 @@ public:
getCompatibleVlnvString()
{ return "xilinx.com:ip:axi_pcie:"; }
bool configureJson(Core& ip, json_t *json_ip);
bool configureJson(Core &ip, json_t *json_ip);
Core* create()
{ return new AxiPciExpressBridge; }

6
fpga/include/villas/fpga/ips/rtds2gpu.hpp
View file

@ -34,16 +34,16 @@ public:
void dump(spdlog::level::level_enum logLevel = spdlog::level::info);
bool startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset);
bool startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset);
size_t getMaxFrameSize();
void dumpDoorbell(uint32_t doorbellRegister) const;
bool doorbellIsValid(const uint32_t& doorbellRegister) const
bool doorbellIsValid(const uint32_t &doorbellRegister) const
{ return reinterpret_cast<const reg_doorbell_t&>(doorbellRegister).is_valid; }
void doorbellReset(uint32_t& doorbellRegister) const
void doorbellReset(uint32_t &doorbellRegister) const
{ doorbellRegister = 0; }
static constexpr const char* registerMemory = "Reg";

8
fpga/include/villas/fpga/ips/switch.hpp
View file

@ -46,11 +46,11 @@ public:
bool init();
bool connectInternal(const std::string& slavePort,
const std::string& masterPort);
bool connectInternal(const std::string &slavePort,
const std::string &masterPort);
private:
int portNameToNum(const std::string& portName);
int portNameToNum(const std::string &portName);
private:
static constexpr const char* PORT_DISABLED = "DISABLED";
@ -77,7 +77,7 @@ public:
getCompatibleVlnvString()
{ return "xilinx.com:ip:axis_switch:"; }
bool configureJson(Core& ip, json_t *json_ip);
bool configureJson(Core &ip, json_t *json_ip);
Core* create()
{ return new AxiStreamSwitch; }

18
fpga/include/villas/fpga/node.hpp
View file

@ -44,14 +44,14 @@ namespace ip {
class StreamVertex : public graph::Vertex {
public:
StreamVertex(const std::string& node, const std::string& port, bool isMaster) :
StreamVertex(const std::string &node, const std::string &port, bool isMaster) :
nodeName(node), portName(port), isMaster(isMaster) {}
std::string getName() const
{ return nodeName + "/" + portName + "(" + (isMaster ? "M" : "S") + ")"; }
friend std::ostream&
operator<< (std::ostream& stream, const StreamVertex& vertex)
operator<< (std::ostream &stream, const StreamVertex &vertex)
{ return stream << vertex.getIdentifier() << ": " << vertex.getName(); }
public:
@ -66,12 +66,12 @@ public:
StreamGraph() : graph::DirectedGraph<StreamVertex>("StreamGraph") {}
std::shared_ptr<StreamVertex>
getOrCreateStreamVertex(const std::string& node,
const std::string& port,
getOrCreateStreamVertex(const std::string &node,
const std::string &port,
bool isMaster)
{
for (auto& vertexEntry : vertices) {
auto& vertex = vertexEntry.second;
for (auto &vertexEntry : vertices) {
auto &vertex = vertexEntry.second;
if (vertex->nodeName == node and vertex->portName == port and vertex->isMaster == isMaster)
return vertex;
}
@ -95,14 +95,12 @@ public:
std::string nodeName;
};
bool connect(const StreamVertex& from, const StreamVertex& to);
const StreamVertex&
getMasterPort(const std::string& name) const
getMasterPort(const std::string &name) const
{ return *portsMaster.at(name); }
const StreamVertex&
getSlavePort(const std::string& name) const
getSlavePort(const std::string &name) const
{ return *portsSlave.at(name); }
// easy-usage assuming that the slave IP to connect to only has one slave

6
fpga/include/villas/fpga/vlnv.hpp
View file

@ -53,14 +53,14 @@ public:
toString() const;
bool
operator==(const Vlnv& other) const;
operator==(const Vlnv &other) const;
bool
operator!=(const Vlnv& other) const
operator!=(const Vlnv &other) const
{ return !(*this == other); }
friend std::ostream&
operator<< (std::ostream& stream, const Vlnv& vlnv)
operator<< (std::ostream &stream, const Vlnv &vlnv)
{
return stream
<< (vlnv.vendor.empty() ? "*" : vlnv.vendor) << ":"

22
fpga/lib/card.cpp
View file

@ -119,10 +119,10 @@ PCIeCardFactory::create()
PCIeCard::~PCIeCard()
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
// unmap all memory blocks
for (auto& mappedMemoryBlock : memoryBlocksMapped) {
for (auto &mappedMemoryBlock : memoryBlocksMapped) {
auto translation = mm.getTranslation(addrSpaceIdDeviceToHost,
mappedMemoryBlock);
@ -137,9 +137,9 @@ PCIeCard::~PCIeCard()
ip::Core::Ptr
PCIeCard::lookupIp(const std::string& name) const
PCIeCard::lookupIp(const std::string &name) const
{
for (auto& ip : ips) {
for (auto &ip : ips) {
if (*ip == name) {
return ip;
}
@ -150,9 +150,9 @@ PCIeCard::lookupIp(const std::string& name) const
ip::Core::Ptr
PCIeCard::lookupIp(const Vlnv& vlnv) const
PCIeCard::lookupIp(const Vlnv &vlnv) const
{
for (auto& ip : ips) {
for (auto &ip : ips) {
if (*ip == vlnv) {
return ip;
}
@ -162,9 +162,9 @@ PCIeCard::lookupIp(const Vlnv& vlnv) const
}
ip::Core::Ptr
PCIeCard::lookupIp(const ip::IpIdentifier& id) const
PCIeCard::lookupIp(const ip::IpIdentifier &id) const
{
for (auto& ip : ips) {
for (auto &ip : ips) {
if (*ip == id) {
return ip;
}
@ -175,15 +175,15 @@ PCIeCard::lookupIp(const ip::IpIdentifier& id) const
bool
PCIeCard::mapMemoryBlock(const MemoryBlock& block)
PCIeCard::mapMemoryBlock(const MemoryBlock &block)
{
if (not vfioContainer->isIommuEnabled()) {
logger->warn("VFIO mapping not supported without IOMMU");
return false;
}
auto& mm = MemoryManager::get();
const auto& addrSpaceId = block.getAddrSpaceId();
auto &mm = MemoryManager::get();
const auto &addrSpaceId = block.getAddrSpaceId();
if (memoryBlocksMapped.find(addrSpaceId) != memoryBlocksMapped.end()) {
// block already mapped

26
fpga/lib/core.cpp
View file

@ -85,7 +85,7 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
// first to be initialized.
vlnvInitializationOrder.reverse();
for (auto& vlnvInitFirst : vlnvInitializationOrder) {
for (auto &vlnvInitFirst : vlnvInitializationOrder) {
// iterate over IPs, if VLNV matches, push to front and remove from list
for (auto it = allIps.begin(); it != allIps.end(); ++it) {
if (vlnvInitFirst == it->getVlnv()) {
@ -99,12 +99,12 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
orderedIps.splice(orderedIps.end(), allIps);
loggerStatic->debug("IP initialization order:");
for (auto& id : orderedIps) {
for (auto &id : orderedIps) {
loggerStatic->debug(" " CLR_BLD("{}"), id.getName());
}
// configure all IPs
for (auto& id : orderedIps) {
for (auto &id : orderedIps) {
loggerStatic->info("Configuring {}", id);
// find the appropriate factory that can create the specified VLNV
@ -162,10 +162,10 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
continue;
}
const std::string& irqControllerName = tokens[0];
const std::string &irqControllerName = tokens[0];
InterruptController* intc = nullptr;
for (auto& configuredIp : configuredIps) {
for (auto &configuredIp : configuredIps) {
if (*configuredIp == irqControllerName) {
intc = dynamic_cast<InterruptController*>(configuredIp.get());
break;
@ -265,12 +265,12 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
}
// Start and check IPs now
for (auto& ip : configuredIps) {
for (auto &ip : configuredIps) {
// Translate all memory blocks that the IP needs to be accessible from
// the process and cache in the instance, so this has not to be done at
// runtime.
for (auto& memoryBlock : ip->getMemoryBlocks()) {
for (auto &memoryBlock : ip->getMemoryBlocks()) {
// construct the global name of this address block
const auto addrSpaceName =
MemoryManager::getSlaveAddrSpaceName(ip->getInstanceName(),
@ -284,7 +284,7 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
ip->slaveAddressSpaces.emplace(memoryBlock, addrSpaceId);
// get the translation to the address space
const auto& translation =
const auto &translation =
MemoryManager::get().getTranslationFromProcess(addrSpaceId);
// cache it in the IP instance only with local name
@ -309,7 +309,7 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
loggerStatic->debug("Initialized IPs:");
for (auto& ip : initializedIps) {
for (auto &ip : initializedIps) {
loggerStatic->debug(" {}", *ip);
}
@ -335,7 +335,7 @@ Core::dump()
CoreFactory*
CoreFactory::lookup(const Vlnv &vlnv)
{
for (auto& ip : plugin::Registry::lookup<CoreFactory>()) {
for (auto &ip : plugin::Registry::lookup<CoreFactory>()) {
if (ip->getCompatibleVlnv() == vlnv)
return ip;
}
@ -345,17 +345,17 @@ CoreFactory::lookup(const Vlnv &vlnv)
uintptr_t
Core::getLocalAddr(const MemoryBlockName& block, uintptr_t address) const
Core::getLocalAddr(const MemoryBlockName &block, uintptr_t address) const
{
// throws exception if block not present
auto& translation = addressTranslations.at(block);
auto &translation = addressTranslations.at(block);
return translation.getLocalAddr(address);
}
InterruptController*
Core::getInterruptController(const std::string& interruptName) const
Core::getInterruptController(const std::string &interruptName) const
{
try {
const IrqPort irq = irqs.at(interruptName);

4
fpga/lib/ips/bram.cpp
View file

@ -29,9 +29,9 @@ namespace ip {
static BramFactory factory;
bool
BramFactory::configureJson(Core& ip, json_t* json_ip)
BramFactory::configureJson(Core &ip, json_t* json_ip)
{
auto& bram = dynamic_cast<Bram&>(ip);
auto &bram = dynamic_cast<Bram&>(ip);
if (json_unpack(json_ip, "{ s: i }", "size", &bram.size) != 0) {
getLogger()->error("Cannot parse 'size'");

16
fpga/lib/ips/dma.cpp
View file

@ -126,7 +126,7 @@ Dma::reset()
bool
Dma::memcpy(const MemoryBlock& src, const MemoryBlock& dst, size_t len)
Dma::memcpy(const MemoryBlock &src, const MemoryBlock &dst, size_t len)
{
if (len == 0)
return true;
@ -151,9 +151,9 @@ Dma::memcpy(const MemoryBlock& src, const MemoryBlock& dst, size_t len)
bool
Dma::write(const MemoryBlock& mem, size_t len)
Dma::write(const MemoryBlock &mem, size_t len)
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
// user has to make sure that memory is accessible, otherwise this will throw
auto translation = mm.getTranslation(busMasterInterfaces[mm2sInterface],
@ -166,9 +166,9 @@ Dma::write(const MemoryBlock& mem, size_t len)
bool
Dma::read(const MemoryBlock& mem, size_t len)
Dma::read(const MemoryBlock &mem, size_t len)
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
// user has to make sure that memory is accessible, otherwise this will throw
auto translation = mm.getTranslation(busMasterInterfaces[s2mmInterface],
@ -351,7 +351,7 @@ Dma::readCompleteSimple()
bool
Dma::makeAccesibleFromVA(const MemoryBlock& mem)
Dma::makeAccesibleFromVA(const MemoryBlock &mem)
{
// only symmetric mapping supported currently
if (isMemoryBlockAccesible(mem, s2mmInterface) and
@ -377,9 +377,9 @@ Dma::makeAccesibleFromVA(const MemoryBlock& mem)
bool
Dma::isMemoryBlockAccesible(const MemoryBlock& mem, const std::string& interface)
Dma::isMemoryBlockAccesible(const MemoryBlock &mem, const std::string &interface)
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
try {
mm.findPath(getMasterAddrSpaceByInterface(interface), mem.getAddrSpaceId());

6
fpga/lib/ips/intc.cpp
View file

@ -41,7 +41,7 @@ static InterruptControllerFactory factory;
InterruptController::~InterruptController()
{
card->vfioDevice->pciMsiDeinit(this->efds);
card->kernel::vfio::Device->pciMsiDeinit(this->efds);
}
bool
@ -49,11 +49,11 @@ InterruptController::init()
{
const uintptr_t base = getBaseAddr(registerMemory);
num_irqs = card->vfioDevice->pciMsiInit(efds);
num_irqs = card->kernel::vfio::Device->pciMsiInit(efds);
if (num_irqs < 0)
return false;
if (not card->vfioDevice->pciMsiFind(nos)) {
if (not card->kernel::vfio::Device->pciMsiFind(nos)) {
return false;
}

10
fpga/lib/ips/pcie.cpp
View file

@ -38,21 +38,21 @@ static AxiPciExpressBridgeFactory factory;
bool
AxiPciExpressBridge::init()
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
// Throw an exception if the is no bus master interface and thus no
// address space we can use for translation -> error
card->addrSpaceIdHostToDevice = busMasterInterfaces.at(axiInterface);
/* Map PCIe BAR0 via VFIO */
const void* bar0_mapped = card->vfioDevice->regionMap(VFIO_PCI_BAR0_REGION_INDEX);
const void* bar0_mapped = card->kernel::vfio::Device->regionMap(VFIO_PCI_BAR0_REGION_INDEX);
if (bar0_mapped == MAP_FAILED) {
logger->error("Failed to mmap() BAR0");
return false;
}
// determine size of BAR0 region
const size_t bar0_size = card->vfioDevice->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX);
const size_t bar0_size = card->kernel::vfio::Device->regionGetSize(VFIO_PCI_BAR0_REGION_INDEX);
// create a mapping from process address space to the FPGA card via vfio
mm.createMapping(reinterpret_cast<uintptr_t>(bar0_mapped),
@ -122,10 +122,10 @@ AxiPciExpressBridge::init()
}
bool
AxiPciExpressBridgeFactory::configureJson(Core& ip, json_t* json_ip)
AxiPciExpressBridgeFactory::configureJson(Core &ip, json_t* json_ip)
{
auto logger = getLogger();
auto& pcie = dynamic_cast<AxiPciExpressBridge&>(ip);
auto &pcie = dynamic_cast<AxiPciExpressBridge&>(ip);
for (auto barType : std::list<std::string>{"axi_bars", "pcie_bars"}) {
json_t* json_bars = json_object_get(json_ip, barType.c_str());

8
fpga/lib/ips/rtds2gpu/gpu2rtds.cpp
View file

@ -15,7 +15,7 @@ bool Gpu2Rtds::init()
{
Hls::init();
auto& registers = addressTranslations.at(registerMemory);
auto &registers = addressTranslations.at(registerMemory);
registerStatus = reinterpret_cast<StatusRegister*>(registers.getLocalAddr(registerStatusOffset));
registerStatusCtrl = reinterpret_cast<StatusControlRegister*>(registers.getLocalAddr(registerStatusCtrlOffset));
@ -55,9 +55,9 @@ void Gpu2Rtds::dump(spdlog::level::level_enum logLevel)
logger->log(logLevel, " Max. frame size: {}", status.max_frame_size);
}
//bool Gpu2Rtds::startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
//bool Gpu2Rtds::startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
//{
// auto& mm = MemoryManager::get();
// auto &mm = MemoryManager::get();
// if (frameSize > maxFrameSize) {
// logger->error("Requested frame size of {} exceeds max. frame size of {}",
@ -123,7 +123,7 @@ Gpu2Rtds::getMaxFrameSize()
//void
//Gpu2Rtds::dumpDoorbell(uint32_t doorbellRegister) const
//{
// auto& doorbell = reinterpret_cast<reg_doorbell_t&>(doorbellRegister);
// auto &doorbell = reinterpret_cast<reg_doorbell_t&>(doorbellRegister);
// logger->info("Doorbell register: {:#08x}", doorbell.value);
// logger->info(" Valid: {}", (doorbell.is_valid ? "yes" : "no"));

6
fpga/lib/ips/rtds2gpu/rtds2gpu.cpp
View file

@ -52,9 +52,9 @@ void Rtds2Gpu::dump(spdlog::level::level_enum logLevel)
logger->log(logLevel, " Max. frame size: {}", status.max_frame_size);
}
bool Rtds2Gpu::startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
bool Rtds2Gpu::startOnce(const MemoryBlock &mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
{
auto& mm = MemoryManager::get();
auto &mm = MemoryManager::get();
if (frameSize > maxFrameSize) {
logger->error("Requested frame size of {} exceeds max. frame size of {}",
@ -108,7 +108,7 @@ Rtds2Gpu::getMaxFrameSize()
void
Rtds2Gpu::dumpDoorbell(uint32_t doorbellRegister) const
{
auto& doorbell = reinterpret_cast<reg_doorbell_t&>(doorbellRegister);
auto &doorbell = reinterpret_cast<reg_doorbell_t&>(doorbellRegister);
logger->info("Doorbell register: {:#08x}", doorbell.value);
logger->info(" Valid: {}", (doorbell.is_valid ? "yes" : "no"));

16
fpga/lib/ips/switch.cpp
View file

@ -70,8 +70,8 @@ AxiStreamSwitch::init()
}
bool
AxiStreamSwitch::connectInternal(const std::string& portSlave,
const std::string& portMaster)
AxiStreamSwitch::connectInternal(const std::string &portSlave,
const std::string &portMaster)
{
// check if slave port exists
try {
@ -129,21 +129,21 @@ AxiStreamSwitch::connectInternal(const std::string& portSlave,
}
int
AxiStreamSwitch::portNameToNum(const std::string& portName)
AxiStreamSwitch::portNameToNum(const std::string &portName)
{
const std::string number = portName.substr(1, 2);
return std::stoi(number);
}
bool
AxiStreamSwitchFactory::configureJson(Core& ip, json_t* json_ip)
AxiStreamSwitchFactory::configureJson(Core &ip, json_t* json_ip)
{
if (not NodeFactory::configureJson(ip, json_ip))
return false;
auto logger = getLogger();
auto& axiSwitch = dynamic_cast<AxiStreamSwitch&>(ip);
auto &axiSwitch = dynamic_cast<AxiStreamSwitch&>(ip);
if (json_unpack(json_ip, "{ s: i }", "num_ports", &axiSwitch.num_ports) != 0) {
logger->error("Cannot parse 'num_ports'");
@ -154,6 +154,6 @@ AxiStreamSwitchFactory::configureJson(Core& ip, json_t* json_ip)
}
} // namespace ip
} // namespace fpga
} // namespace villas
} /* namespace ip */
} /* namespace fpga */
} /* namespace villas */

14
fpga/lib/node.cpp
View file

@ -39,9 +39,9 @@ StreamGraph
Node::streamGraph;
bool
NodeFactory::configureJson(Core& ip, json_t* json_ip)
NodeFactory::configureJson(Core &ip, json_t* json_ip)
{
auto& Node = dynamic_cast<ip::Node&>(ip);
auto &Node = dynamic_cast<ip::Node&>(ip);
auto logger = getLogger();
json_t* json_ports = json_object_get(json_ip, "ports");
@ -115,7 +115,7 @@ Node::getLoopbackPorts() const
return { "", "" };
}
bool Node::connect(const StreamVertex& from, const StreamVertex& to)
bool Node::connect(const StreamVertex &from, const StreamVertex &to)
{
if (from.nodeName != getInstanceName()) {
logger->error("Cannot connect from a foreign StreamVertex: {}", from);
@ -192,8 +192,8 @@ Node::loopbackPossible() const
}
bool
Node::connectInternal(const std::string& slavePort,
const std::string& masterPort)
Node::connectInternal(const std::string &slavePort,
const std::string &masterPort)
{
(void) slavePort;
(void) masterPort;
@ -206,8 +206,8 @@ bool
Node::connectLoopback()
{
auto ports = getLoopbackPorts();
const auto& portMaster = portsMaster[ports.first];
const auto& portSlave = portsSlave[ports.second];
const auto &portMaster = portsMaster[ports.first];
const auto &portSlave = portsSlave[ports.second];
logger->debug("master port: {}", ports.first);
logger->debug("slave port: {}", ports.second);

2
fpga/src/fpga.c
View file

@ -28,7 +28,7 @@
#include <villas/log.h>
#include <villas/utils.hpp>
#include <villas/kernel/pci.h>
#include <villas/kernel/pci.hpp>
#include <villas/kernel/kernel.hpp>
#include <villas/fpga/card.h>

6
fpga/src/villas-fpga-pipe.cpp
View file

@ -64,7 +64,7 @@ void setupColorHandling()
}
std::shared_ptr<fpga::PCIeCard>
setupFpgaCard(const std::string& configFile, const std::string& fpgaName)
setupFpgaCard(const std::string &configFile, const std::string &fpgaName)
{
if (pci_init(&pci) != 0) {
logger->error("Cannot initialize PCI");
@ -104,7 +104,7 @@ setupFpgaCard(const std::string& configFile, const std::string& fpgaName)
// create all FPGA card instances using the corresponding plugin
auto cards = fpgaCardPlugin->make(fpgas, &pci, vfioContainer);
for (auto& fpgaCard : cards) {
for (auto &fpgaCard : cards) {
if (fpgaCard->name == fpgaName) {
return fpgaCard;
}
@ -192,7 +192,7 @@ int main(int argc, char* argv[])
size_t memIdx = 0;
for (auto& value: values) {
for (auto &value: values) {
if (value.empty()) continue;
const int32_t number = std::stoi(value);

4
fpga/tests/dma.cpp
View file

@ -39,7 +39,7 @@ Test(fpga, dma, .description = "DMA")
std::list<std::shared_ptr<fpga::ip::Dma>> dmaIps;
for (auto& ip : state.cards.front()->ips) {
for (auto &ip : state.cards.front()->ips) {
if (*ip == fpga::Vlnv("xilinx.com:ip:axi_dma:")) {
auto dma = std::dynamic_pointer_cast<fpga::ip::Dma>(ip);
dmaIps.push_back(dma);
@ -47,7 +47,7 @@ Test(fpga, dma, .description = "DMA")
}
size_t count = 0;
for (auto& dma : dmaIps) {
for (auto &dma : dmaIps) {
logger->info("Testing {}", *dma);
if (not dma->loopbackPossible()) {

2
fpga/tests/fifo.cpp
View file

@ -40,7 +40,7 @@ Test(fpga, fifo, .description = "FIFO")
auto logger = logging.get("unit-test:fifo");
for (auto& ip : state.cards.front()->ips) {
for (auto &ip : state.cards.front()->ips) {
// skip non-fifo IPs
if (*ip != fpga::Vlnv("xilinx.com:ip:axi_fifo_mm_s:"))
continue;

2
fpga/tests/fpga.cpp
View file

@ -59,7 +59,7 @@ static void init()
ret = pci_init(&pci);
cr_assert_eq(ret, 0, "Failed to initialize PCI sub-system");
auto vfioContainer = VfioContainer::create();
auto vfioContainer = kernel::vfio::Container::create();
/* Parse FPGA configuration */
char *fn = getenv("TEST_CONFIG");

2
fpga/tests/global.hpp
View file

@ -29,7 +29,7 @@
class FpgaState {
public:
// list of all available FPGA cards, only first will be tested at the moment
villas::fpga::CardList cards;
villas::fpga::PCIeCard::List cards;
};
// global state to be shared by unittests

22
fpga/tests/gpu.cpp
View file

@ -44,7 +44,7 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests")
{
auto logger = logging.get("unit-test:dma");
auto& card = state.cards.front();
auto &card = state.cards.front();
auto gpuPlugin = Plugin::Registry<GpuFactory>("cuda");
cr_assert_not_null(gpuPlugin, "No GPU plugin found");
@ -53,10 +53,10 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests")
cr_assert(gpus.size() > 0, "No GPUs found");
// just get first cpu
auto& gpu = gpus.front();
auto &gpu = gpus.front();
size_t count = 0;
for (auto& ip : card->ips) {
for (auto &ip : card->ips) {
// skip non-dma IPs
if (*ip != fpga::Vlnv("xilinx.com:ip:axi_bram_ctrl:"))
continue;
@ -97,17 +97,17 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests")
gpu->makeAccessibleToPCIeAndVA(gpuMem1.getMemoryBlock());
// auto& src = bram0;
// auto& dst = bram1;
// auto &src = bram0;
// auto &dst = bram1;
// auto& src = hostRam0;
// auto& dst = hostRam1;
// auto &src = hostRam0;
// auto &dst = hostRam1;
auto& src = dmaRam0;
// auto& dst = dmaRam1;
auto &src = dmaRam0;
// auto &dst = dmaRam1;
// auto& src = gpuMem0;
auto& dst = gpuMem1;
// auto &src = gpuMem0;
auto &dst = gpuMem1;
std::list<std::pair<std::string, std::function<void()>>> memcpyFuncs = {

2
fpga/tests/rtds.cpp
View file

@ -49,7 +49,7 @@ Test(fpga, rtds, .description = "RTDS")
std::list<villas::fpga::ip::Rtds*> rtdsIps;
std::list<villas::fpga::ip::Dma*> dmaIps;
for (auto& ip : state.cards.front()->ips) {
for (auto &ip : state.cards.front()->ips) {
if (*ip == villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")) {
auto rtds = reinterpret_cast<villas::fpga::ip::Rtds*>(ip.get());
rtdsIps.push_back(rtds);

12
fpga/tests/rtds2gpu.cpp
View file

@ -72,7 +72,7 @@ Test(fpga, rtds2gpu_loopback_dma, .description = "Rtds2Gpu")
{
auto logger = logging.get("unit-test:rtds2gpu");
for (auto& ip : state.cards.front()->ips) {
for (auto &ip : state.cards.front()->ips) {
if (*ip != fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:rtds2gpu:"))
continue;
@ -191,11 +191,11 @@ Test(fpga, rtds2gpu_rtt_cpu, .description = "Rtds2Gpu RTT via CPU")
cr_assert_not_null(gpu2rtds, "No Gpu2Rtds IP found");
cr_assert_not_null(rtds2gpu, "No Rtds2Gpu IP not found");
for (auto& ip : state.cards.front()->ips) {
for (auto &ip : state.cards.front()->ips) {
if (*ip != fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:"))
continue;
auto& rtds = dynamic_cast<fpga::ip::Rtds&>(*ip);
auto &rtds = dynamic_cast<fpga::ip::Rtds&>(*ip);
logger->info("Testing {}", rtds);
auto dmaRam = HostDmaRam::getAllocator().allocate<uint32_t>(SAMPLE_COUNT + 1);
@ -269,7 +269,7 @@ Test(fpga, rtds2gpu_rtt_gpu, .description = "Rtds2Gpu RTT via GPU")
cr_assert(gpus.size() > 0, "No GPUs found");
// just get first cpu
auto& gpu = gpus.front();
auto &gpu = gpus.front();
// allocate memory on GPU and make accessible by to PCIe/FPGA
auto gpuRam = gpu->getAllocator().allocate<uint32_t>(SAMPLE_COUNT + 1);
@ -291,11 +291,11 @@ Test(fpga, rtds2gpu_rtt_gpu, .description = "Rtds2Gpu RTT via GPU")
// auto doorbellInCpu = reinterpret_cast<reg_doorbell_t*>(&gpuRam[DOORBELL_OFFSET]);
for (auto& ip : state.cards.front()->ips) {
for (auto &ip : state.cards.front()->ips) {
if (*ip != fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:"))
continue;
auto& rtds = dynamic_cast<fpga::ip::Rtds&>(*ip);
auto &rtds = dynamic_cast<fpga::ip::Rtds&>(*ip);
logger->info("Testing {}", rtds);

2
fpga/tests/rtds_rtt.c
View file

@ -42,7 +42,7 @@ Test(fpga, rtds_rtt, .description = "RTDS: tight rtt")
std::list<villas::fpga::ip::Dma*> dmaIps;
/* Get IP cores */
for (auto& ip : state.cards.front()->ips) {
for (auto &ip : state.cards.front()->ips) {
if (*ip == villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")) {
auto rtds = reinterpret_cast<villas::fpga::ip::Rtds*>(ip.get());
rtdsIps.push_back(rtds);

2
fpga/tests/timer.cpp
View file

@ -34,7 +34,7 @@ Test(fpga, timer, .description = "Timer Counter")
auto logger = villas::logging.get("unit-test:timer");
size_t count = 0;
for (auto& ip : state.cards.front()->ips) {
for (auto &ip : state.cards.front()->ips) {
// skip non-timer IPs
if (*ip != villas::fpga::Vlnv("xilinx.com:ip:axi_timer:")) {
continue;