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https://git.rwth-aachen.de/acs/public/villas/node/
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update hardware submodule and move hwdef-parse script into hardware repo
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3 changed files with 2 additions and 8416 deletions
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Subproject commit 2eaf71991d7b29e46105dbd0fa27bc3a130f16f9
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Subproject commit 86f84f9cb7833a43e6449365d14fd6487deb57fd
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#!/usr/bin/env python3
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"""
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Author: Daniel Krebs <github@daniel-krebs.net>
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Copyright: 2017-2018, Institute for Automation of Complex Power Systems, EONERC
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License: GNU General Public License (version 3)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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"""
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from lxml import etree
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import zipfile
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import sys
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import re
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import json
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whitelist = [
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[ 'xilinx.com', 'ip', 'axi_timer' ],
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[ 'xilinx.com', 'ip', 'axis_switch' ],
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[ 'xilinx.com', 'ip', 'axi_fifo_mm_s' ],
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[ 'xilinx.com', 'ip', 'axi_dma' ],
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[ 'acs.eonerc.rwth-aachen.de', 'user', 'axi_pcie_intc' ],
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[ 'acs.eonerc.rwth-aachen.de', 'user', 'rtds_axis' ],
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[ 'acs.eonerc.rwth-aachen.de', 'hls' ],
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[ 'acs.eonerc.rwth-aachen.de', 'sysgen' ],
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[ 'xilinx.com', 'ip', 'axi_gpio' ],
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[ 'xilinx.com', 'ip', 'axi_bram_ctrl' ],
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[ 'xilinx.com', 'ip', 'axis_data_fifo' ],
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[ 'xilinx.com', 'ip', 'axi_pcie' ],
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[ 'xilinx.com', 'hls', 'rtds2gpu' ],
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[ 'xilinx.com', 'hls', 'mem' ]
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]
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# List of VLNI ids of AXI4-Stream infrastructure IP cores which do not alter data
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# see PG085 (AXI4-Stream Infrastructure IP Suite v2.2)
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axi_converter_whitelist = [
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[ 'xilinx.com', 'ip', 'axis_subset_converter' ],
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[ 'xilinx.com', 'ip', 'axis_clock_converter' ],
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[ 'xilinx.com', 'ip', 'axis_register_slice' ],
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[ 'xilinx.com', 'ip', 'axis_dwidth_converter' ],
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[ 'xilinx.com', 'ip', 'axis_register_slice' ]
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]
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opponent = {
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'MASTER' : ('SLAVE', 'TARGET'),
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'SLAVE' : ('MASTER', 'INITIATOR'),
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'INITIATOR' : ('TARGET', 'SLAVE'),
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'TARGET' : ('INITIATOR', 'MASTER')
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}
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def port_trace(root, signame, idx):
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pass
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def port_find_driver(root, signame):
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pass
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def bus_trace(root, busname, type, whitelist):
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module = root.xpath('.//MODULE[.//BUSINTERFACE[@BUSNAME="{}" and (@TYPE="{}" or @TYPE="{}")]]'.format(busname, type[0], type[1]))
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vlnv = module[0].get('VLNV')
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instance = module[0].get('INSTANCE')
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if vlnv_match(vlnv, whitelist):
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return instance, busname
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elif vlnv_match(vlnv, axi_converter_whitelist):
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next_bus = module[0].xpath('.//BUSINTERFACE[@TYPE="{}" or @TYPE="{}"]'.format(opponent[type[0]][0], opponent[type[0]][1]))
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next_busname = next_bus[0].get('BUSNAME')
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return bus_trace(root, next_busname, type, whitelist)
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else:
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raise TypeError('Unsupported AXI4-Stream IP core: %s (%s)' % (instance, vlnv))
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def vlnv_match(vlnv, whitelist):
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c = vlnv.split(':')
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for w in whitelist:
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if c[:len(w)] == w:
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return True
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return False
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def remove_prefix(text, prefix):
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return text[text.startswith(prefix) and len(prefix):]
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def sanitize_name(name):
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name = remove_prefix(name, 'S_')
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name = remove_prefix(name, 'M_')
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name = remove_prefix(name, 'AXI_')
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name = remove_prefix(name, 'AXIS_')
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return name
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if len(sys.argv) < 2:
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print('Usage: {} path/to/*.hwdef'.format(sys.argv[0]))
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print(' {} path/to/*.xml'.format(sys.argv[0]))
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sys.exit(1)
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try:
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# read .hwdef which is actually a zip-file
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zip = zipfile.ZipFile(sys.argv[1], 'r')
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hwh = zip.read('top.hwh')
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except:
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f = open(sys.argv[1], 'r')
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hwh = f.read()
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# parse .hwh file which is actually XML
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try:
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root = etree.XML(hwh)
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except:
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print('Bad format of "{}"! Did you choose the right file?'.format(sys.argv[1]))
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sys.exit(1)
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ips = {}
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# find all whitelisted modules
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modules = root.find('.//MODULES')
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for module in modules:
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instance = module.get('INSTANCE')
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vlnv = module.get('VLNV')
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# Ignroing unkown
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if not vlnv_match(vlnv, whitelist):
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continue
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ips[instance] = {
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'vlnv' : vlnv
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}
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# populate memory view
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mmap = module.find('.//MEMORYMAP')
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if not mmap:
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continue
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mem = ips[instance].setdefault('memory-view', {})
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for mrange in mmap:
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mem_interface = mrange.get('MASTERBUSINTERFACE')
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mem_instance = mrange.get('INSTANCE')
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mem_block = mrange.get('ADDRESSBLOCK')
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_interface = mem.setdefault(mem_interface, {})
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_instance = _interface.setdefault(mem_instance, {})
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_block = _instance.setdefault(mem_block, {})
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_block['baseaddr'] = int(mrange.get('BASEVALUE'), 16)
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_block['highaddr'] = int(mrange.get('HIGHVALUE'), 16)
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_block['size'] = _block['highaddr'] - _block['baseaddr'] + 1
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# find AXI-Stream switch port mapping
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switch = root.find('.//MODULE[@MODTYPE="axis_switch"]')
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busifs = switch.find('.//BUSINTERFACES')
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switch_ports = 0
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for busif in busifs:
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if busif.get('VLNV') != 'xilinx.com:interface:axis:1.0':
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continue
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switch_ports += 1
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busname = busif.get('BUSNAME')
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name = busif.get('NAME')
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type = busif.get('TYPE')
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r = re.compile('(M|S)([0-9]+)_AXIS')
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m = r.search(name)
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port = int(m.group(2))
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switch_ip_ports = ips[switch.get('INSTANCE')].setdefault('ports', [])
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ep, busname_ep = bus_trace(root, busname, opponent[type], whitelist)
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if ep in ips:
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ports = ips[ep].setdefault('ports', [])
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ports.append({
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'role': opponent[type][0].lower(),
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'target': '{}:{}'.format(switch.get('INSTANCE'), name)
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})
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module_ep = root.find('.//MODULE[@INSTANCE="{}"]'.format(ep))
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busif_ep = module_ep.find('.//BUSINTERFACE[@BUSNAME="{}"]'.format(busname_ep))
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if not busif_ep:
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print("cannot find businterface: {}".format(busname_ep))
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sys.exit(1)
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busif_name = ports[-1]['name'] = sanitize_name(busif_ep.get('NAME'))
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ports[-1]['name'] = busif_name
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switch_ip_ports.append({
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'role': type.lower(),
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'target': '{}:{}'.format(ep, busif_name),
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'name': name
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})
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# set number of master/slave port pairs for switch
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ips[switch.get('INSTANCE')]['num_ports'] = int(switch_ports / 2)
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# find Interrupt assignments
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intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]')
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intr = intc.xpath('.//PORT[@NAME="intr" and @DIR="I"]')[0]
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concat = root.xpath('.//MODULE[@MODTYPE="xlconcat" and .//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(intr.get('SIGNAME')))[0]
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ports = concat.xpath('.//PORT[@DIR="I"]')
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for port in ports:
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name = port.get('NAME')
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signame = port.get('SIGNAME')
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# Skip unconnected IRQs
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if not signame:
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continue
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r = re.compile('In([0-9+])')
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m = r.search(name)
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irq = int(m.group(1))
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ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
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instance = ip.get('INSTANCE')
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vlnv = ip.get('VLNV')
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modtype = ip.get('MODTYPE')
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originators = []
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# follow one level of OR gates merging interrupts (may be generalized later)
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if modtype == 'util_vector_logic':
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logic_op = ip.xpath('.//PARAMETER[@NAME="C_OPERATION"]')[0]
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if logic_op.get('VALUE') == 'or':
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# hardware interrupts sharing the same IRQ at the controller
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ports = ip.xpath('.//PORT[@DIR="I"]')
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for port in ports:
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signame = port.get('SIGNAME')
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ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
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instance = ip.get('INSTANCE')
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originators.append((instance, signame))
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else:
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# consider this instance as originator
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originators.append((instance, signame))
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for instance, signame in originators:
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ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
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port = ip.xpath('.//PORT[@SIGNAME="{}" and @DIR="O"]'.format(signame))[0]
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irqname = port.get('NAME')
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if instance in ips:
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irqs = ips[instance].setdefault('irqs', {})
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irqs[irqname] = '{}:{}'.format(intc.get('INSTANCE'), irq)
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# Find BRAM storage depths (size)
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brams = root.xpath('.//MODULE[@MODTYPE="axi_bram_ctrl"]')
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for bram in brams:
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instance = bram.get('INSTANCE')
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width = bram.find('.//PARAMETER[@NAME="DATA_WIDTH"]').get('VALUE')
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depth = bram.find('.//PARAMETER[@NAME="MEM_DEPTH"]').get('VALUE')
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size = int(width) * int(depth) / 8
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if instance in ips:
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ips[instance]['size'] = int(size)
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pcies = root.xpath('.//MODULE[@MODTYPE="axi_pcie"]')
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for pcie in pcies:
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instance = pcie.get('INSTANCE')
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axi_bars = ips[instance].setdefault('axi_bars', {})
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pcie_bars = ips[instance].setdefault('pcie_bars', {})
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for from_bar, to_bar, from_bars in (('AXIBAR', 'PCIEBAR', axi_bars), ('PCIEBAR', 'AXIBAR', pcie_bars)):
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from_bar_num = int(pcie.find('.//PARAMETER[@NAME="C_{}_NUM"]'.format(from_bar)).get('VALUE'))
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for i in range(0, from_bar_num):
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from_bar_to_bar_offset = int(pcie.find('.//PARAMETER[@NAME="C_{}2{}_{}"]'.format(from_bar, to_bar, i)).get('VALUE'), 16)
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from_bars['BAR{}'.format(i)] = { 'translation': from_bar_to_bar_offset }
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if from_bar == 'AXIBAR':
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axi_bar_lo = int(pcie.find('.//PARAMETER[@NAME="C_{}_{}"]'.format(from_bar, i)).get('VALUE'), 16)
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axi_bar_hi = int(pcie.find('.//PARAMETER[@NAME="C_{}_HIGHADDR_{}"]'.format(from_bar, i)).get('VALUE'), 16)
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axi_bar_size = axi_bar_hi - axi_bar_lo + 1
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axi_bar = from_bars['BAR{}'.format(i)]
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axi_bar['baseaddr'] = axi_bar_lo
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axi_bar['highaddr'] = axi_bar_hi
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axi_bar['size'] = axi_bar_size
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print(json.dumps(ips, indent=2))
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1
fpga/scripts/hwdef-parse.py
Symbolic link
1
fpga/scripts/hwdef-parse.py
Symbolic link
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@ -0,0 +1 @@
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../hardware/scripts/hwdef-parse.py
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