Mirrors/VILLASnode
1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-09 00:00:00 +01:00
Code Issues Releases Wiki Activity

scripts/hwdef-parse: update ports format

Browse source
This commit is contained in:
daniel-k 2018-01-17 16:49:33 +01:00
parent 4db0a98082
commit 935fa847aa
1 changed files with 6 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
fpga/scripts/hwdef-parse.py
View file

@ -170,8 +170,12 @@ for busif in busifs:
ep = bus_trace(root, busname, opponent[type], whitelist)
if ep in ips:
ports = ips[ep].setdefault('ports', {})
ports[type.lower()] = port
ports = ips[ep].setdefault('ports', [])
ports.append({
'role': type.lower(),
'target': switch.get('INSTANCE'),
'port': port
})
# find Interrupt assignments
intc = root.find('.//MODULE[@MODTYPE="axi_pcie_intc"]')