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synced 2025-03-09 00:00:00 +01:00
fpga: turn off all interrupts when using polling
this improves the latency by at least 4 us in my setup. Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
parent
69b5425c0c
commit
937cdda11f
1 changed files with 13 additions and 18 deletions
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@ -119,7 +119,9 @@ void Dma::setupScatterGatherRingRx(uintptr_t physAddr, uintptr_t virtAddr) {
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XAxiDma_SelectCyclicMode(&xDma, XAXIDMA_DEVICE_TO_DMA, 1);
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}
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// Enable completion interrupt
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XAxiDma_IntrEnable(&xDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
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if (!polling) {
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XAxiDma_IntrEnable(&xDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
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}
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// Start the RX channel
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ret = XAxiDma_BdRingStart(rxRingPtr);
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if (ret != XST_SUCCESS)
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@ -155,8 +157,9 @@ void Dma::setupScatterGatherRingTx(uintptr_t physAddr, uintptr_t virtAddr) {
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throw RuntimeError("Failed to clone TX ring BD: {}", ret);
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// Enable completion interrupt
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XAxiDma_IntrEnable(&xDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
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if (!polling) {
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XAxiDma_IntrEnable(&xDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
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}
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// Start the TX channel
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ret = XAxiDma_BdRingStart(txRingPtr);
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if (ret != XST_SUCCESS)
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@ -410,10 +413,6 @@ Dma::Completion Dma::writeCompleteScatterGather() {
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// PCIe address space, yet. The subsequent DMA Controller management can be done in a
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// separate thread to keep latencies in this thread extremly low. We know that we have
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// received one BD.
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do {
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// This takes 1.5 us
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irqStatus = XAxiDma_BdRingGetIrq(txRing);
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} while (!(irqStatus & XAXIDMA_IRQ_IOC_MASK));
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} else {
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c.interrupts = irqs[mm2sInterrupt].irqController->waitForInterrupt(
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irqs[mm2sInterrupt].num);
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@ -432,8 +431,8 @@ Dma::Completion Dma::writeCompleteScatterGather() {
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// Acknowledge the interrupt
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if (!polling) {
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irqStatus = XAxiDma_BdRingGetIrq(txRing);
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XAxiDma_BdRingAckIrq(txRing, irqStatus);
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}
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XAxiDma_BdRingAckIrq(txRing, irqStatus);
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if (c.bds == 0) {
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c.bytes = 0;
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@ -490,10 +489,6 @@ Dma::Completion Dma::readCompleteScatterGather() {
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// PCIe address space, yet. The subsequent DMA Controller management can be done in a
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// separate thread to keep latencies in this thread extremly low. We know that we have
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// received one BD.
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do {
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// This takes 1.5 us
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irqStatus = XAxiDma_BdRingGetIrq(rxRing);
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} while (!(irqStatus & XAXIDMA_IRQ_IOC_MASK));
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intrs = 1;
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} else {
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intrs = irqs[s2mmInterrupt].irqController->waitForInterrupt(
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@ -517,13 +512,13 @@ Dma::Completion Dma::readCompleteScatterGather() {
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}
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if (!polling) {
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irqStatus = XAxiDma_BdRingGetIrq(rxRing);
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XAxiDma_BdRingAckIrq(rxRing, irqStatus);
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if (!(irqStatus & XAXIDMA_IRQ_IOC_MASK)) {
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logger->error("Expected IOC interrupt but IRQ status is: {:#x}",
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irqStatus);
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return c;
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}
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}
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XAxiDma_BdRingAckIrq(rxRing, irqStatus);
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if (!(irqStatus & XAXIDMA_IRQ_IOC_MASK)) {
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logger->error("Expected IOC interrupt but IRQ status is: {:#x}", irqStatus);
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return c;
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}
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// Wait until the data has been received by the RX channel.
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if ((c.bds = XAxiDma_BdRingFromHw(rxRing, readCoalesce, &bd)) <
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readCoalesce) {
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