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fix wrong usage of reinterpret_cast in ips and tests

This commit is contained in:
Daniel Krebs 2018-05-30 14:02:25 +02:00
parent 010e0c3681
commit 93fe1390d6
7 changed files with 7 additions and 7 deletions

View file

@ -9,7 +9,7 @@ static BramFactory factory;
bool
BramFactory::configureJson(IpCore& ip, json_t* json_ip)
{
auto& bram = reinterpret_cast<Bram&>(ip);
auto& bram = dynamic_cast<Bram&>(ip);
if(json_unpack(json_ip, "{ s: i }", "size", &bram.size) != 0) {
getLogger()->error("Cannot parse 'size'");

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@ -125,7 +125,7 @@ bool
AxiPciExpressBridgeFactory::configureJson(IpCore& ip, json_t* json_ip)
{
auto logger = getLogger();
auto& pcie = reinterpret_cast<AxiPciExpressBridge&>(ip);
auto& pcie = dynamic_cast<AxiPciExpressBridge&>(ip);
for(auto barType : std::list<std::string>{"axi_bars", "pcie_bars"}) {
json_t* json_bars = json_object_get(json_ip, barType.c_str());

View file

@ -143,7 +143,7 @@ AxiStreamSwitchFactory::configureJson(IpCore& ip, json_t* json_ip)
auto logger = getLogger();
auto& axiSwitch = reinterpret_cast<AxiStreamSwitch&>(ip);
auto& axiSwitch = dynamic_cast<AxiStreamSwitch&>(ip);
if(json_unpack(json_ip, "{ s: i }", "num_ports", &axiSwitch.num_ports) != 0) {
logger->error("Cannot parse 'num_ports'");

View file

@ -24,7 +24,7 @@ Test(fpga, dma, .description = "DMA")
logger->info("Testing {}", *ip);
auto dma = reinterpret_cast<villas::fpga::ip::Dma&>(*ip);
auto dma = dynamic_cast<villas::fpga::ip::Dma&>(*ip);
if(not dma.loopbackPossible()) {
logger->info("Loopback test not possible for {}", *ip);

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@ -47,7 +47,7 @@ Test(fpga, fifo, .description = "FIFO")
logger->info("Testing {}", *ip);
auto fifo = reinterpret_cast<villas::fpga::ip::Fifo&>(*ip);
auto fifo = dynamic_cast<villas::fpga::ip::Fifo&>(*ip);
if(not fifo.connectLoopback()) {
continue;

View file

@ -40,7 +40,7 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests")
logger->info("Testing {}", *ip);
auto bram = reinterpret_cast<villas::fpga::ip::Bram*>(ip.get());
auto bram = dynamic_cast<villas::fpga::ip::Bram*>(ip.get());
cr_assert_not_null(bram, "Couldn't find BRAM");
count++;

View file

@ -46,7 +46,7 @@ Test(fpga, timer, .description = "Timer Counter")
count++;
auto timer = reinterpret_cast<villas::fpga::ip::Timer&>(*ip);
auto timer = dynamic_cast<villas::fpga::ip::Timer&>(*ip);
logger->info("Test simple waiting");
timer.start(timer.getFrequency() / 10);