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etc/json: update config file with current output of hwdef-parse

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This commit is contained in:
Daniel Krebs 2018-02-13 10:03:16 +01:00 • committed by Steffen Vogel
parent 912c3729d4
commit 95adaad32f
1 changed files with 177 additions and 60 deletions
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237
fpga/etc/fpga.json
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@ -28,74 +28,114 @@
"ips": {
"bram_0_axi_bram_ctrl_0": {
"vlnv": "xilinx.com:ip:axi_bram_ctrl:4.0",
"s_axi_baseaddr": 0,
"s_axi_highaddr": 8191,
"size": 8192
},
"hier_0_axi_dma_axi_dma_0": {
"vlnv": "xilinx.com:ip:axi_dma:7.1",
"memory-view": {
"SG": {
"M_AXI_SG": {
"bram_0_axi_bram_ctrl_0": {
"baseaddr": 0,
"highaddr": 8191
"Mem0": {
"baseaddr": 0,
"highaddr": 8191,
"size": 8192
}
},
"hier_0_axi_dma_axi_dma_1": {
"baseaddr": 8192,
"highaddr": 12287
"Reg": {
"baseaddr": 8192,
"highaddr": 12287,
"size": 4096
}
},
"hier_0_axi_dma_axi_dma_0": {
"baseaddr": 12288,
"highaddr": 16383
"Reg": {
"baseaddr": 12288,
"highaddr": 16383,
"size": 4096
}
},
"timer_0_axi_timer_0": {
"baseaddr": 16384,
"highaddr": 20479
"Reg": {
"baseaddr": 16384,
"highaddr": 20479,
"size": 4096
}
},
"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
"baseaddr": 20480,
"highaddr": 24575
"Reg": {
"baseaddr": 20480,
"highaddr": 24575,
"size": 4096
}
},
"hier_0_axi_fifo_mm_s_0": {
"baseaddr": 49152,
"highaddr": 57343
"Mem0": {
"baseaddr": 24576,
"highaddr": 28671,
"size": 4096
},
"Mem1": {
"baseaddr": 49152,
"highaddr": 57343,
"size": 8192
}
},
"pcie_0_axi_reset_0": {
"baseaddr": 28672,
"highaddr": 32767
"Reg": {
"baseaddr": 28672,
"highaddr": 32767,
"size": 4096
}
},
"hier_0_rtds_axis_0": {
"baseaddr": 32768,
"highaddr": 36863
"reg0": {
"baseaddr": 32768,
"highaddr": 36863,
"size": 4096
}
},
"hier_0_hls_dft_0": {
"baseaddr": 36864,
"highaddr": 40959
"Reg": {
"baseaddr": 36864,
"highaddr": 40959,
"size": 4096
}
},
"pcie_0_axi_pcie_intc_0": {
"baseaddr": 45056,
"highaddr": 49151
"Reg": {
"baseaddr": 45056,
"highaddr": 49151,
"size": 4096
}
},
"pcie_0_axi_pcie_0": {
"baseaddr": 268435456,
"highaddr": 536870911
"CTL0": {
"baseaddr": 268435456,
"highaddr": 536870911,
"size": 268435456
}
}
},
"MM2S": {
"M_AXI_MM2S": {
"pcie_0_axi_pcie_0": {
"baseaddr": 2147483648,
"highaddr": 4294967295
"BAR0": {
"baseaddr": 2147483648,
"highaddr": 4294967295,
"size": 2147483648
}
}
},
"S2MM": {
"M_AXI_S2MM": {
"pcie_0_axi_pcie_0": {
"baseaddr": 2147483648,
"highaddr": 4294967295
"BAR0": {
"baseaddr": 2147483648,
"highaddr": 4294967295,
"size": 2147483648
}
}
}
},
"baseaddr": 12288,
"highaddr": 16383,
"ports": [
{
"role": "initiator",
@ -112,21 +152,25 @@
"hier_0_axi_dma_axi_dma_1": {
"vlnv": "xilinx.com:ip:axi_dma:7.1",
"memory-view": {
"MM2S": {
"M_AXI_MM2S": {
"pcie_0_axi_pcie_0": {
"baseaddr": 2147483648,
"highaddr": 4294967295
"BAR0": {
"baseaddr": 2147483648,
"highaddr": 4294967295,
"size": 2147483648
}
}
},
"S2MM": {
"M_AXI_S2MM": {
"pcie_0_axi_pcie_0": {
"baseaddr": 2147483648,
"highaddr": 4294967295
"BAR0": {
"baseaddr": 2147483648,
"highaddr": 4294967295,
"size": 2147483648
}
}
}
},
"baseaddr": 8192,
"highaddr": 12287,
"ports": [
{
"role": "initiator",
@ -142,10 +186,6 @@
},
"hier_0_axi_fifo_mm_s_0": {
"vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1",
"baseaddr": 24576,
"highaddr": 28671,
"axi4_baseaddr": 49152,
"axi4_highaddr": 57343,
"ports": [
{
"role": "master",
@ -164,8 +204,6 @@
},
"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
"vlnv": "xilinx.com:ip:axis_switch:1.1",
"baseaddr": 20480,
"highaddr": 24575,
"ports": [
{
"role": "initiator",
@ -188,12 +226,10 @@
"name": "S04_AXIS"
}
],
"num_ports": 14
"num_ports": 7
},
"hier_0_hls_dft_0": {
"vlnv": "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0",
"s_axi_ctrl_baseaddr": 36864,
"s_axi_ctrl_highaddr": 40959,
"ports": [
{
"role": "master",
@ -209,8 +245,6 @@
},
"hier_0_rtds_axis_0": {
"vlnv": "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0",
"baseaddr": 32768,
"highaddr": 36863,
"ports": [
{
"role": "master",
@ -229,20 +263,103 @@
"irq_case": "pcie_0_axi_pcie_intc_0:7"
}
},
"pcie_0_axi_pcie_0": {
"vlnv": "xilinx.com:ip:axi_pcie:2.8",
"memory-view": {
"M_AXI": {
"bram_0_axi_bram_ctrl_0": {
"Mem0": {
"baseaddr": 0,
"highaddr": 8191,
"size": 8192
}
},
"hier_0_axi_dma_axi_dma_1": {
"Reg": {
"baseaddr": 8192,
"highaddr": 12287,
"size": 4096
}
},
"hier_0_axi_dma_axi_dma_0": {
"Reg": {
"baseaddr": 12288,
"highaddr": 16383,
"size": 4096
}
},
"timer_0_axi_timer_0": {
"Reg": {
"baseaddr": 16384,
"highaddr": 20479,
"size": 4096
}
},
"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
"Reg": {
"baseaddr": 20480,
"highaddr": 24575,
"size": 4096
}
},
"hier_0_axi_fifo_mm_s_0": {
"Mem0": {
"baseaddr": 24576,
"highaddr": 28671,
"size": 4096
},
"Mem1": {
"baseaddr": 49152,
"highaddr": 57343,
"size": 8192
}
},
"pcie_0_axi_reset_0": {
"Reg": {
"baseaddr": 28672,
"highaddr": 32767,
"size": 4096
}
},
"hier_0_rtds_axis_0": {
"reg0": {
"baseaddr": 32768,
"highaddr": 36863,
"size": 4096
}
},
"hier_0_hls_dft_0": {
"Reg": {
"baseaddr": 36864,
"highaddr": 40959,
"size": 4096
}
},
"pcie_0_axi_pcie_intc_0": {
"Reg": {
"baseaddr": 45056,
"highaddr": 49151,
"size": 4096
}
},
"pcie_0_axi_pcie_0": {
"CTL0": {
"baseaddr": 268435456,
"highaddr": 536870911,
"size": 268435456
}
}
}
}
},
"pcie_0_axi_pcie_intc_0": {
"vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0",
"baseaddr": 45056,
"highaddr": 49151
"vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0"
},
"pcie_0_axi_reset_0": {
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
"baseaddr": 28672,
"highaddr": 32767
"vlnv": "xilinx.com:ip:axi_gpio:2.0"
},
"timer_0_axi_timer_0": {
"vlnv": "xilinx.com:ip:axi_timer:2.0",
"baseaddr": 16384,
"highaddr": 20479,
"irqs": {
"generateout0": "pcie_0_axi_pcie_intc_0:0"
}