Mirrors/VILLASnode
1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-09 00:00:00 +01:00
Code Issues Releases Wiki Activity

fpga: Apply suggestions from code review

Browse source 
Co-authored-by: Steffen Vogel <steffen.vogel@opal-rt.com>
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
Niklas Eiling 2024-11-05 10:48:55 +01:00
parent 35a1d72e0d
commit 9814543d6c
2 changed files with 9 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
fpga/lib/ips/axis_cache.cpp
View file

@ -1,4 +1,6 @@
/* Driver for AXI Stream read cache. This module is used to lower latency of
/* Driver for AXI Stream read cache.
*
* This module is used to lower latency of
* a DMA Scatter Gather engine's descriptor fetching. The driver allows for
* invalidating the cache.
*
@ -27,7 +29,8 @@ bool AxisCache::check() {
logger->debug("Checking register interface: Base address: 0x{:08x}",
getBaseAddr(registerMemory));
uint32_t buf;
// we shouldn't change the rate register, because this can lead to hardware fault, so start at 1
// We should not change the rate register, because this can lead to hardware fault, so start at 1
for (size_t i = 1; i < registerNum; i++) {
setRegister(i, static_cast<uint32_t>(0x00FF00FF));
}

5
fpga/lib/ips/dino.cpp
View file

@ -157,6 +157,7 @@ void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
uint32_t dinoTimerVal = static_cast<uint32_t>(dinoClk / sampleRate) - 1;
uint32_t dinoDacDelayCycles = static_cast<uint32_t>(dinoClk * dinoDacDelay);
double rateError = dinoClk / (dinoTimerVal + 1) - sampleRate;
// Timer value for generating ADC trigger signal
reg->setRegister(dinoRegisterTimer, dinoTimerVal);
@ -166,7 +167,7 @@ void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
// the DAC. Offset is a value to be added to the result of the multiplication.
// All values are IEE 754 single precision floating point values.
// Calibration for ADC filter with C=330pF and R=2,2kOhm
// FIXME: These values should be read from the FPGA or configured via the configuration file.
// TODO: These values should be read from the FPGA or configured via the configuration file.
reg->setRegister(dinoRegisterAdcScale,
0.0016874999385349976F); // Scale factor for ADC value
reg->setRegister(dinoRegisterAdcOffset,
@ -177,12 +178,14 @@ void DinoAdc::setRegisterConfig(std::shared_ptr<Register> reg,
32772.159015058445F); // Offset for DAC value
reg->setRegister(dinoRegisterDacExternalTrig,
(uint32_t)0x0); // External trigger for DAC
if (dinoTimerVal > dinoDacDelayCycles) {
reg->setRegister(dinoRegisterTimerPreThresh,
dinoTimerVal - dinoDacDelayCycles);
} else {
reg->setRegister(dinoRegisterTimerPreThresh, dinoTimerVal);
}
uint32_t rate = reg->getRegister(dinoRegisterTimer);
float adcScale = reg->getRegisterFloat(dinoRegisterAdcScale);
float adcOffset = reg->getRegisterFloat(dinoRegisterAdcOffset);