mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
added and fixed a bunch of unit tests
This commit is contained in:
parent
411b9dd326
commit
99a142bb6b
6 changed files with 262 additions and 175 deletions
|
|
@ -4,58 +4,57 @@
|
|||
* @copyright 2017, Institute for Automation of Complex Power Systems, EONERC
|
||||
*********************************************************************************/
|
||||
|
||||
#include <unistd.h>
|
||||
|
||||
#include <criterion/criterion.h>
|
||||
#include <criterion/logging.h>
|
||||
|
||||
#include <villas/utils.h>
|
||||
#include <villas/advio.h>
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
/** This URI points to a Sciebo share which contains some test files.
|
||||
* The Sciebo share is read/write accessible via WebDAV. */
|
||||
#define BASE_URI "https://1Nrd46fZX8HbggT:badpass@rwth-aachen.sciebo.de/public.php/webdav/node/tests"
|
||||
|
||||
#define TEST_DATA_DOWNLOAD "ook4iekohC2Teegoghu6ayoo1OThooregheebaet8Zod1angah0che7quai4ID7A"
|
||||
#define TEST_DATA_UPLOAD "jaeke4quei3oongeebuchahz9aabahkie8oor3Gaejem1AhSeph5Ahch9ohz3eeh"
|
||||
#define TEST_DATA_APPEND1 "xa5gieTohlei9iu1uVaePae6Iboh3eeheeme5iejue5sheshae4uzisha9Faesei"
|
||||
#define TEST_DATA_APPEND2 "bitheeRae7igee2miepahJaefoGad1Ooxeif0Mooch4eojoumueYahn4ohc9poo2"
|
||||
|
||||
Test(advio, download)
|
||||
{
|
||||
AFILE *af;
|
||||
int ret;
|
||||
size_t len;
|
||||
char buffer[64];
|
||||
char expect[64] = "ook4iekohC2Teegoghu6ayoo1OThooregheebaet8Zod1angah0che7quai4ID7A";
|
||||
|
||||
af = afopen(BASE_URI "/download" , "r");
|
||||
cr_assert(af, "Failed to download file");
|
||||
|
||||
len = afread(buffer, 1, sizeof(buffer), af);
|
||||
cr_assert_gt(len, 0, "len=%zu, feof=%u", len, afeof(af));
|
||||
|
||||
cr_assert_gt(len, 0);
|
||||
cr_assert_arr_eq(buffer, TEST_DATA_DOWNLOAD, strlen(TEST_DATA_DOWNLOAD));
|
||||
|
||||
cr_assert_arr_eq(buffer, expect, sizeof(expect));
|
||||
|
||||
ret = afclose(af);
|
||||
cr_assert_eq(ret, 0, "Failed to close/upload file");
|
||||
cr_assert_eq(ret, 0, "Failed to close file");
|
||||
}
|
||||
|
||||
Test(advio, upload)
|
||||
{
|
||||
AFILE *af;
|
||||
int ret;
|
||||
|
||||
size_t len;
|
||||
size_t tlen = strlen(TEST_DATA_UPLOAD);
|
||||
|
||||
char buffer[tlen];
|
||||
char upload[64];
|
||||
char buffer[64];
|
||||
|
||||
/* Get some random data to upload */
|
||||
len = read_random(upload, sizeof(upload));
|
||||
cr_assert_eq(len, sizeof(upload));
|
||||
|
||||
/* Open file for writing */
|
||||
af = afopen(BASE_URI "/upload", "w+");
|
||||
cr_assert(af, "Failed to download file");
|
||||
|
||||
len = afwrite(TEST_DATA_UPLOAD, 1, strlen(TEST_DATA_UPLOAD), af);
|
||||
cr_assert_eq(len, strlen(TEST_DATA_UPLOAD));
|
||||
len = afwrite(upload, 1, sizeof(upload), af);
|
||||
cr_assert_eq(len, sizeof(upload));
|
||||
|
||||
ret = afclose(af);
|
||||
cr_assert_eq(ret, 0, "Failed to close/upload file");
|
||||
|
|
@ -64,10 +63,10 @@ Test(advio, upload)
|
|||
af = afopen(BASE_URI "/upload", "r");
|
||||
cr_assert(af, "Failed to download file");
|
||||
|
||||
len = afread(buffer, 1, strlen(TEST_DATA_UPLOAD), af);
|
||||
cr_assert_eq(len, strlen(TEST_DATA_UPLOAD));
|
||||
len = afread(buffer, 1, sizeof(upload), af);
|
||||
cr_assert_eq(len, sizeof(upload));
|
||||
|
||||
cr_assert_arr_eq(buffer, TEST_DATA_UPLOAD, len);
|
||||
cr_assert_arr_eq(buffer, upload, len);
|
||||
|
||||
ret = afclose(af);
|
||||
cr_assert(ret == 0, "Failed to close file");
|
||||
|
|
@ -76,20 +75,31 @@ Test(advio, upload)
|
|||
Test(advio, append)
|
||||
{
|
||||
AFILE *af;
|
||||
|
||||
int ret;
|
||||
|
||||
size_t len;
|
||||
size_t tlen = strlen(TEST_DATA_APPEND1) + strlen(TEST_DATA_APPEND2);
|
||||
|
||||
char buffer[tlen];
|
||||
char append1[64] = "xa5gieTohlei9iu1uVaePae6Iboh3eeheeme5iejue5sheshae4uzisha9Faesei";
|
||||
char append2[64] = "bitheeRae7igee2miepahJaefoGad1Ooxeif0Mooch4eojoumueYahn4ohc9poo2";
|
||||
char expect[128] = "xa5gieTohlei9iu1uVaePae6Iboh3eeheeme5iejue5sheshae4uzisha9FaeseibitheeRae7igee2miepahJaefoGad1Ooxeif0Mooch4eojoumueYahn4ohc9poo2";
|
||||
char buffer[128];
|
||||
|
||||
/* Open file for writing first chunk */
|
||||
af = afopen(BASE_URI "/append", "w+");
|
||||
cr_assert(af, "Failed to download file");
|
||||
|
||||
len = afwrite(TEST_DATA_APPEND1, 1, strlen(TEST_DATA_APPEND1), af);
|
||||
cr_assert_eq(len, strlen(TEST_DATA_APPEND1));
|
||||
/* The append file might already exist and be not empty from a previous run. */
|
||||
ret = ftruncate(afileno(af), 0);
|
||||
cr_assert_eq(ret, 0);
|
||||
|
||||
char c;
|
||||
fseek(af->file, 0, SEEK_SET);
|
||||
if (af->file) {
|
||||
while ((c = getc(af->file)) != EOF)
|
||||
putchar(c);
|
||||
}
|
||||
|
||||
len = afwrite(append1, 1, sizeof(append1), af);
|
||||
cr_assert_eq(len, sizeof(append1));
|
||||
|
||||
ret = afclose(af);
|
||||
cr_assert_eq(ret, 0, "Failed to close/upload file");
|
||||
|
|
@ -98,8 +108,8 @@ Test(advio, append)
|
|||
af = afopen(BASE_URI "/append", "a");
|
||||
cr_assert(af, "Failed to download file");
|
||||
|
||||
len = afwrite(TEST_DATA_APPEND1, 1, strlen(TEST_DATA_APPEND2), af);
|
||||
cr_assert_eq(len, strlen(TEST_DATA_APPEND2));
|
||||
len = afwrite(append2, 1, sizeof(append2), af);
|
||||
cr_assert_eq(len, sizeof(append2));
|
||||
|
||||
ret = afclose(af);
|
||||
cr_assert_eq(ret, 0, "Failed to close/upload file");
|
||||
|
|
@ -108,12 +118,11 @@ Test(advio, append)
|
|||
af = afopen(BASE_URI "/append", "r");
|
||||
cr_assert(af, "Failed to download file");
|
||||
|
||||
len = afread(buffer, 1, tlen, af);
|
||||
cr_assert_eq(len, tlen);
|
||||
len = afread(buffer, 1, sizeof(buffer), af);
|
||||
cr_assert_eq(len, sizeof(buffer));
|
||||
|
||||
ret = afclose(af);
|
||||
cr_assert(ret == 0, "Failed to close file");
|
||||
|
||||
cr_assert_arr_eq(buffer, TEST_DATA_APPEND1, strlen(TEST_DATA_APPEND1));
|
||||
cr_assert_arr_eq(buffer + strlen(TEST_DATA_APPEND1), TEST_DATA_APPEND2, strlen(TEST_DATA_APPEND2));
|
||||
cr_assert_arr_eq(buffer, expect, sizeof(expect));
|
||||
}
|
||||
|
|
@ -32,23 +32,39 @@
|
|||
#define CPU_HZ 3392389000
|
||||
|
||||
static struct fpga_card *card;
|
||||
static struct super_node sn;
|
||||
static struct super_node sn = { .state = STATE_DESTROYED };
|
||||
static struct pci pci;
|
||||
static struct vfio_container vc;
|
||||
|
||||
static void init()
|
||||
{
|
||||
int ret;
|
||||
int argc = 1;
|
||||
char *argv[] = { "tests" };
|
||||
config_setting_t *cfg_root;
|
||||
|
||||
super_node_parse_uri(&sn, TEST_CONFIG);
|
||||
ret = super_node_init(&sn);
|
||||
cr_assert_eq(ret, 0, "Failed to initialize Supernode");
|
||||
|
||||
ret = super_node_parse_uri(&sn, TEST_CONFIG);
|
||||
cr_assert_eq(ret, 0, "Failed to parse configuration");
|
||||
|
||||
ret = super_node_check(&sn);
|
||||
cr_assert_eq(ret, 0, "Failed to check configuration");
|
||||
|
||||
cfg_root = config_root_setting(&sn.cfg);
|
||||
cr_assert_neq(cfg_root, NULL);
|
||||
|
||||
ret = fpga_init(argc, argv, cfg_root);
|
||||
cr_assert_eq(ret, 0, "Failed to initilize FPGA");
|
||||
ret = pci_init(&pci);
|
||||
cr_assert_eq(ret, 0, "Failed to initialize PCI sub-system");
|
||||
|
||||
ret = vfio_init(&vc);
|
||||
cr_assert_eq(ret, 0, "Failed to initiliaze VFIO sub-system");
|
||||
|
||||
/* Parse FPGA configuration */
|
||||
ret = fpga_parse_cards(cfg_root);
|
||||
cr_assert_eq(ret, 0, "Failed to parse FPGA config");
|
||||
|
||||
card = fpga_lookup_card("vc707");
|
||||
cr_assert(card, "FPGA card not found");
|
||||
|
||||
if (criterion_options.logging_threshold < CRITERION_IMPORTANT)
|
||||
fpga_card_dump(card);
|
||||
|
|
@ -77,8 +93,7 @@ Test(fpga, intc, .description = "Interrupt Controller")
|
|||
cr_assert(card->intc);
|
||||
|
||||
ret = intc_enable(card->intc, 0xFF00, 0);
|
||||
if (ret)
|
||||
error("Failed to enable interrupt");
|
||||
cr_assert_eq(ret, 0, "Failed to enable interrupt");
|
||||
|
||||
/* Fake IRQs in software by writing to ISR */
|
||||
XIntc_Out32((uintptr_t) card->map + card->intc->baseaddr + XIN_ISR_OFFSET, 0xFF00);
|
||||
|
|
@ -91,8 +106,7 @@ Test(fpga, intc, .description = "Interrupt Controller")
|
|||
isr = XIntc_In32((uintptr_t) card->map + card->intc->baseaddr + XIN_ISR_OFFSET);
|
||||
|
||||
ret = intc_disable(card->intc, 0xFF00);
|
||||
if (ret)
|
||||
error("Failed to disable interrupt");
|
||||
cr_assert_eq(ret, 0, "Failed to disable interrupt");
|
||||
|
||||
cr_assert_eq(isr & 0xFF00, 0); /* ISR should get cleared by MSI_Grant_signal */
|
||||
}
|
||||
|
|
@ -102,36 +116,35 @@ Test(fpga, xsg, .description = "XSG: multiply_add")
|
|||
int ret;
|
||||
double factor, err = 0;
|
||||
|
||||
struct fpga_ip *xsg, *dma;
|
||||
struct fpga_ip *ip, *dma;
|
||||
struct model_param *p;
|
||||
struct dma_mem mem;
|
||||
|
||||
xsg = fpga_vlnv_lookup(&card->ips, &(struct fpga_vlnv) { NULL, "sysgen", "xsg_multiply", NULL });
|
||||
ip = fpga_vlnv_lookup(&card->ips, &(struct fpga_vlnv) { NULL, "sysgen", "xsg_multiply", NULL });
|
||||
cr_assert(ip);
|
||||
|
||||
dma = fpga_vlnv_lookup(&card->ips, &(struct fpga_vlnv) { "xilinx.com", "ip", "axi_dma", NULL });
|
||||
cr_assert(dma);
|
||||
|
||||
/* Check if required IP is available on FPGA */
|
||||
cr_assert_neq(!dma || !xsg || !dma, 0);
|
||||
struct model *model = (struct model *) ip->_vd;
|
||||
|
||||
p = list_lookup(&xsg->model.parameters, "factor");
|
||||
p = list_lookup(&model->parameters, "factor");
|
||||
if (!p)
|
||||
error("Missing parameter 'factor' for model '%s'", xsg->name);
|
||||
error("Missing parameter 'factor' for model '%s'", ip->name);
|
||||
|
||||
ret = model_param_read(p, &factor);
|
||||
if (ret)
|
||||
error("Failed to read parameter 'factor' from model '%s'", xsg->name);
|
||||
cr_assert_eq(ret, 0, "Failed to read parameter 'factor' from model '%s'", ip->name);
|
||||
|
||||
info("Model param: factor = %f", factor);
|
||||
|
||||
ret = switch_connect(card->sw, dma, xsg);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_connect(card->sw, xsg, dma);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_connect(card->sw, dma, ip);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = switch_connect(card->sw, ip, dma);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = dma_alloc(dma, &mem, 0x1000, 0);
|
||||
if (ret)
|
||||
error("Failed to allocate DMA memory");
|
||||
cr_assert_eq(ret, 0, "Failed to allocate DMA memory");
|
||||
|
||||
float *src = (float *) mem.base_virt;
|
||||
float *dst = (float *) mem.base_virt + 0x800;
|
||||
|
|
@ -140,24 +153,21 @@ Test(fpga, xsg, .description = "XSG: multiply_add")
|
|||
src[i] = 1.1 * (i+1);
|
||||
|
||||
ret = dma_ping_pong(dma, (char *) src, (char *) dst, 6 * sizeof(float));
|
||||
if (ret)
|
||||
error("Failed to to ping pong DMA transfer: %d", ret);
|
||||
cr_assert_eq(ret, 0, "Failed to to ping pong DMA transfer: %d", ret);
|
||||
|
||||
for (int i = 0; i < 6; i++)
|
||||
err += abs(factor * src[i] - dst[i]);
|
||||
|
||||
info("Error after FPGA operation: err = %f", err);
|
||||
|
||||
ret = switch_disconnect(card->sw, dma, xsg);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_disconnect(card->sw, xsg, dma);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_disconnect(card->sw, dma, ip);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = switch_disconnect(card->sw, ip, dma);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = dma_free(dma, &mem);
|
||||
if (ret)
|
||||
error("Failed to release DMA memory");
|
||||
cr_assert_eq(ret, 0, "Failed to release DMA memory");
|
||||
|
||||
cr_assert(err < 1e-3);
|
||||
}
|
||||
|
|
@ -174,15 +184,13 @@ Test(fpga, hls_dft, .description = "HLS: hls_dft")
|
|||
cr_assert(hls && rtds);
|
||||
|
||||
ret = intc_enable(card->intc, (1 << rtds->irq), 0);
|
||||
if (ret)
|
||||
error("Failed to enable interrupt");
|
||||
cr_assert_eq(ret, 0, "Failed to enable interrupt");
|
||||
|
||||
ret = switch_connect(card->sw, rtds, hls);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = switch_connect(card->sw, hls, rtds);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
while(1) {
|
||||
/* Dump RTDS AXI Stream state */
|
||||
|
|
@ -206,11 +214,10 @@ Test(fpga, hls_dft, .description = "HLS: hls_dft")
|
|||
#endif
|
||||
|
||||
ret = switch_disconnect(card->sw, rtds, hls);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = switch_disconnect(card->sw, hls, rtds);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
}
|
||||
|
||||
Test(fpga, fifo, .description = "FIFO")
|
||||
|
|
@ -224,12 +231,10 @@ Test(fpga, fifo, .description = "FIFO")
|
|||
cr_assert(fifo);
|
||||
|
||||
ret = intc_enable(card->intc, (1 << fifo->irq), 0);
|
||||
if (ret)
|
||||
error("Failed to enable interrupt");
|
||||
cr_assert_eq(ret, 0, "Failed to enable interrupt");
|
||||
|
||||
ret = switch_connect(card->sw, fifo, fifo);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
/* Get some random data to compare */
|
||||
memset(dst, 0, sizeof(dst));
|
||||
|
|
@ -246,12 +251,10 @@ Test(fpga, fifo, .description = "FIFO")
|
|||
error("Failed to read from FIFO");
|
||||
|
||||
ret = intc_disable(card->intc, (1 << fifo->irq));
|
||||
if (ret)
|
||||
error("Failed to disable interrupt");
|
||||
cr_assert_eq(ret, 0, "Failed to disable interrupt");
|
||||
|
||||
ret = switch_disconnect(card->sw, fifo, fifo);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
/* Compare data */
|
||||
cr_assert_eq(memcmp(src, dst, sizeof(src)), 0);
|
||||
|
|
@ -262,15 +265,19 @@ Test(fpga, dma, .description = "DMA")
|
|||
int ret = -1;
|
||||
struct dma_mem mem, src, dst;
|
||||
|
||||
list_foreach(struct fpga_ip *dma, &card->ips) { INDENT
|
||||
if (fpga_vlnv_cmp(&dma->vlnv, &(struct fpga_vlnv) { "xilinx.com", "ip", "axi_dma", NULL }))
|
||||
for (size_t i = 0; i < list_length(&card->ips); i++) { INDENT
|
||||
struct fpga_ip *dm = list_at(&card->ips, i);
|
||||
|
||||
if (fpga_vlnv_cmp(&dm->vlnv, &(struct fpga_vlnv) { "xilinx.com", "ip", "axi_dma", NULL }))
|
||||
continue; /* skip non DMA IP cores */
|
||||
|
||||
struct dma *dma = (struct dma *) dm->_vd;
|
||||
|
||||
/* Simple DMA can only transfer up to 4 kb due to
|
||||
* PCIe page size burst limitation */
|
||||
ssize_t len2, len = dma->dma.inst.HasSg ? 64 << 20 : 1 << 2;
|
||||
ssize_t len2, len = dma->inst.HasSg ? 64 << 20 : 1 << 2;
|
||||
|
||||
ret = dma_alloc(dma, &mem, 2 * len, 0);
|
||||
ret = dma_alloc(dm, &mem, 2 * len, 0);
|
||||
cr_assert_eq(ret, 0);
|
||||
|
||||
ret = dma_mem_split(&mem, &src, &dst);
|
||||
|
|
@ -281,37 +288,31 @@ Test(fpga, dma, .description = "DMA")
|
|||
if (len2 != len)
|
||||
serror("Failed to get random data");
|
||||
|
||||
int irq_mm2s = dma->irq;
|
||||
int irq_s2mm = dma->irq + 1;
|
||||
int irq_mm2s = dm->irq;
|
||||
int irq_s2mm = dm->irq + 1;
|
||||
|
||||
ret = intc_enable(card->intc, (1 << irq_mm2s) | (1 << irq_s2mm), 0);
|
||||
if (ret)
|
||||
error("Failed to enable interrupt");
|
||||
cr_assert_eq(ret, 0, "Failed to enable interrupt");
|
||||
|
||||
ret = switch_connect(card->sw, dma, dma);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_connect(card->sw, dm, dm);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
/* Start transfer */
|
||||
ret = dma_ping_pong(dma, src.base_phys, dst.base_phys, dst.len);
|
||||
if (ret)
|
||||
error("DMA ping pong failed");
|
||||
ret = dma_ping_pong(dm, src.base_phys, dst.base_phys, dst.len);
|
||||
cr_assert_eq(ret, 0, "DMA ping pong failed");
|
||||
|
||||
ret = memcmp(src.base_virt, dst.base_virt, src.len);
|
||||
|
||||
info("DMA %s (%s): %s", dma->name, dma->dma.inst.HasSg ? "scatter-gather" : "simple", ret ? RED("failed") : GRN("passed"));
|
||||
info("DMA %s (%s): %s", dm->name, dma->inst.HasSg ? "scatter-gather" : "simple", ret ? RED("failed") : GRN("passed"));
|
||||
|
||||
ret = switch_disconnect(card->sw, dma, dma);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_disconnect(card->sw, dm, dm);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = intc_disable(card->intc, (1 << irq_mm2s) | (1 << irq_s2mm));
|
||||
if (ret)
|
||||
error("Failed to disable interrupt");
|
||||
cr_assert_eq(ret, 0, "Failed to disable interrupt");
|
||||
|
||||
ret = dma_free(dma, &mem);
|
||||
if (ret)
|
||||
error("Failed to release DMA memory");
|
||||
ret = dma_free(dm, &mem);
|
||||
cr_assert_eq(ret, 0, "Failed to release DMA memory");
|
||||
}
|
||||
|
||||
cr_assert_eq(ret, 0);
|
||||
|
|
@ -320,22 +321,24 @@ Test(fpga, dma, .description = "DMA")
|
|||
Test(fpga, timer, .description = "Timer Counter")
|
||||
{
|
||||
int ret;
|
||||
struct fpga_ip *tmr;
|
||||
struct fpga_ip *ip;
|
||||
struct timer *tmr;
|
||||
|
||||
tmr = fpga_vlnv_lookup(&card->ips, &(struct fpga_vlnv) { "xilinx.com", "ip", "axi_timer", NULL });
|
||||
cr_assert(tmr);
|
||||
ip = fpga_vlnv_lookup(&card->ips, &(struct fpga_vlnv) { "xilinx.com", "ip", "axi_timer", NULL });
|
||||
cr_assert(ip);
|
||||
|
||||
XTmrCtr *xtmr = &tmr->timer.inst;
|
||||
tmr = (struct timer *) ip->_vd;
|
||||
|
||||
XTmrCtr *xtmr = &tmr->inst;
|
||||
|
||||
ret = intc_enable(card->intc, (1 << tmr->irq), 0);
|
||||
if (ret)
|
||||
error("Failed to enable interrupt");
|
||||
ret = intc_enable(card->intc, (1 << ip->irq), 0);
|
||||
cr_assert_eq(ret, 0, "Failed to enable interrupt");
|
||||
|
||||
XTmrCtr_SetOptions(xtmr, 0, XTC_EXT_COMPARE_OPTION | XTC_DOWN_COUNT_OPTION);
|
||||
XTmrCtr_SetResetValue(xtmr, 0, FPGA_AXI_HZ / 125);
|
||||
XTmrCtr_Start(xtmr, 0);
|
||||
|
||||
uint64_t counter = intc_wait(card->intc, tmr->irq);
|
||||
uint64_t counter = intc_wait(card->intc, ip->irq);
|
||||
info("Got IRQ: counter = %ju", counter);
|
||||
|
||||
if (counter == 1)
|
||||
|
|
@ -343,9 +346,8 @@ Test(fpga, timer, .description = "Timer Counter")
|
|||
else
|
||||
warn("Counter was not 1");
|
||||
|
||||
intc_disable(card->intc, (1 << tmr->irq));
|
||||
if (ret)
|
||||
error("Failed to disable interrupt");
|
||||
intc_disable(card->intc, (1 << ip->irq));
|
||||
cr_assert_eq(ret, 0, "Failed to disable interrupt");
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -353,56 +355,47 @@ Test(fpga, timer, .description = "Timer Counter")
|
|||
Test(fpga, rtds_rtt, .description = "RTDS: tight rtt")
|
||||
{
|
||||
int ret;
|
||||
struct fpga_ip *dma, *rtds;
|
||||
struct fpga_ip *ip, *rtds;
|
||||
struct dma_mem buf;
|
||||
size_t recvlen;
|
||||
|
||||
/* Get IP cores */
|
||||
rtds = fpga_vlnv_lookup(&card->ips, &(struct fpga_vlnv) { "acs.eonerc.rwth-aachen.de", "user", "rtds_axis", NULL });
|
||||
dma = list_lookup(&card->ips, "dma_1");
|
||||
cr_assert(rtds);
|
||||
|
||||
ip = fpga_vlnv_lookup(&card->ips, &(struct fpga_vlnv) { "xilinx.com", "ip", "axi_dma", NULL });
|
||||
cr_assert(ip);
|
||||
|
||||
/* Check if required IP is available on FPGA */
|
||||
cr_assert (dma && rtds);
|
||||
ret = switch_connect(card->sw, rtds, ip);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = switch_connect(card->sw, rtds, dma);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_connect(card->sw, dma, rtds);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_connect(card->sw, ip, rtds);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = dma_alloc(dma, &buf, 0x100, 0);
|
||||
if (ret)
|
||||
error("Failed to allocate DMA memory");
|
||||
ret = dma_alloc(ip, &buf, 0x100, 0);
|
||||
cr_assert_eq(ret, 0, "Failed to allocate DMA memory");
|
||||
|
||||
while (1) {
|
||||
|
||||
ret = dma_read(dma, buf.base_phys, buf.len);
|
||||
if (ret)
|
||||
error("Failed to start DMA read: %d", ret);
|
||||
ret = dma_read(ip, buf.base_phys, buf.len);
|
||||
cr_assert_eq(ret, 0, "Failed to start DMA read: %d", ret);
|
||||
|
||||
ret = dma_read_complete(dma, NULL, &recvlen);
|
||||
if (ret)
|
||||
error("Failed to complete DMA read: %d", ret);
|
||||
ret = dma_read_complete(ip, NULL, &recvlen);
|
||||
cr_assert_eq(ret, 0, "Failed to complete DMA read: %d", ret);
|
||||
|
||||
ret = dma_write(dma, buf.base_phys, recvlen);
|
||||
if (ret)
|
||||
error("Failed to start DMA write: %d", ret);
|
||||
ret = dma_write(ip, buf.base_phys, recvlen);
|
||||
cr_assert_eq(ret, 0, "Failed to start DMA write: %d", ret);
|
||||
|
||||
ret = dma_write_complete(dma, NULL, NULL);
|
||||
if (ret)
|
||||
error("Failed to complete DMA write: %d", ret);
|
||||
ret = dma_write_complete(ip, NULL, NULL);
|
||||
cr_assert_eq(ret, 0, "Failed to complete DMA write: %d", ret);
|
||||
}
|
||||
|
||||
ret = switch_disconnect(card->sw, rtds, dma);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_disconnect(card->sw, rtds, ip);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = switch_disconnect(card->sw, dma, rtds);
|
||||
if (ret)
|
||||
error("Failed to configure switch");
|
||||
ret = switch_disconnect(card->sw, ip, rtds);
|
||||
cr_assert_eq(ret, 0, "Failed to configure switch");
|
||||
|
||||
ret = dma_free(dma, &buf);
|
||||
if (ret)
|
||||
error("Failed to release DMA memory");
|
||||
ret = dma_free(ip, &buf);
|
||||
cr_assert_eq(ret, 0, "Failed to release DMA memory");
|
||||
}
|
||||
|
|
@ -20,7 +20,7 @@ struct data {
|
|||
|
||||
Test(list, list_lookup)
|
||||
{
|
||||
struct list l;
|
||||
struct list l = { .state = STATE_DESTROYED };
|
||||
|
||||
list_init(&l);
|
||||
|
||||
|
|
@ -42,26 +42,26 @@ Test(list, list_lookup)
|
|||
|
||||
Test(list, list_search)
|
||||
{
|
||||
struct list l;
|
||||
struct list l = { .state = STATE_DESTROYED };
|
||||
|
||||
list_init(&l);
|
||||
|
||||
/* Fill list */
|
||||
for (int i = 0; i < ARRAY_LEN(nouns); i++)
|
||||
list_push(&l, nouns[i]);
|
||||
|
||||
cr_assert_eq(list_length(&l), ARRAY_LEN(nouns));
|
||||
|
||||
/* Declare on stack! */
|
||||
char positive[] = "woman";
|
||||
char negative[] = "dinosaurrier";
|
||||
|
||||
char *found = (char *) list_search(&l, (cmp_cb_t) strcmp, positive);
|
||||
|
||||
char *found = list_search(&l, (cmp_cb_t) strcmp, positive);
|
||||
cr_assert_not_null(found);
|
||||
cr_assert_eq(found, nouns[13]);
|
||||
cr_assert_eq(found, nouns[13], "found = %p, nouns[13] = %p", found, nouns[13]);
|
||||
cr_assert_str_eq(found, positive);
|
||||
|
||||
char *not_found = (char *) list_search(&l, (cmp_cb_t) strcmp, negative);
|
||||
|
||||
cr_assert_null(not_found);
|
||||
|
||||
list_destroy(&l, NULL, false);
|
||||
|
|
@ -82,7 +82,7 @@ static int dtor(void *ptr)
|
|||
|
||||
Test(list, destructor)
|
||||
{
|
||||
struct list l;
|
||||
struct list l = { .state = STATE_DESTROYED };
|
||||
struct content elm = { .destroyed = 0 };
|
||||
|
||||
list_init(&l);
|
||||
|
|
@ -102,7 +102,8 @@ static int compare(const void *a, const void *b) {
|
|||
Test(list, basics)
|
||||
{
|
||||
intptr_t i;
|
||||
struct list l;
|
||||
int ret;
|
||||
struct list l = { .state = STATE_DESTROYED };
|
||||
|
||||
list_init(&l);
|
||||
|
||||
|
|
@ -131,13 +132,16 @@ Test(list, basics)
|
|||
i--;
|
||||
}
|
||||
|
||||
cr_assert(list_contains(&l, (void *) 55));
|
||||
ret = list_contains(&l, (void *) 55);
|
||||
cr_assert(ret);
|
||||
|
||||
list_remove(&l, (void *) 55);
|
||||
|
||||
cr_assert(!list_contains(&l, (void *) 55));
|
||||
ret = list_contains(&l, (void *) 55);
|
||||
cr_assert(!ret);
|
||||
|
||||
list_destroy(&l, NULL, false);
|
||||
|
||||
cr_assert_eq(list_length(&l), -1, "List not properly destroyed: l.length = %zd", l.length);
|
||||
ret = list_length(&l);
|
||||
cr_assert_eq(ret, -1, "List not properly destroyed: l.length = %zd", l.length);
|
||||
}
|
||||
80
tests/unit/mapping.c
Normal file
80
tests/unit/mapping.c
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/** Unit tests for sample value mapping.
|
||||
*
|
||||
* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
|
||||
* @copyright 2017, Institute for Automation of Complex Power Systems, EONERC
|
||||
*********************************************************************************/
|
||||
|
||||
#include <criterion/criterion.h>
|
||||
|
||||
#include "mapping.h"
|
||||
|
||||
Test(mapping, parse)
|
||||
{
|
||||
int ret;
|
||||
struct mapping_entry m;
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "ts.origin");
|
||||
cr_assert_eq(ret, 0);
|
||||
cr_assert_eq(m.type, MAPPING_TYPE_TIMESTAMP);
|
||||
cr_assert_eq(m.timestamp.id, MAPPING_TIMESTAMP_ORIGIN);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "hdr.sequence");
|
||||
cr_assert_eq(ret, 0);
|
||||
cr_assert_eq(m.type, MAPPING_TYPE_HEADER);
|
||||
cr_assert_eq(m.header.id, MAPPING_HEADER_SEQUENCE);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "stats.owd.mean");
|
||||
cr_assert_eq(ret, 0);
|
||||
cr_assert_eq(m.type, MAPPING_TYPE_STATS);
|
||||
cr_assert_eq(m.stats.id, STATS_OWD);
|
||||
cr_assert_eq(m.stats.type, MAPPING_STATS_TYPE_MEAN);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "data[1-2]");
|
||||
cr_assert_eq(ret, 0);
|
||||
cr_assert_eq(m.type, MAPPING_TYPE_DATA);
|
||||
cr_assert_eq(m.data.offset, 1);
|
||||
cr_assert_eq(m.length, 2);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "data[5-5]");
|
||||
cr_assert_eq(ret, 0);
|
||||
cr_assert_eq(m.type, MAPPING_TYPE_DATA);
|
||||
cr_assert_eq(m.data.offset, 5);
|
||||
cr_assert_eq(m.length, 1);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "data[22]");
|
||||
cr_assert_eq(ret, 0);
|
||||
cr_assert_eq(m.type, MAPPING_TYPE_DATA);
|
||||
cr_assert_eq(m.data.offset, 22);
|
||||
cr_assert_eq(m.length, 1);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "data[]");
|
||||
cr_assert_neq(ret, 0);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "data[1.1-2f]");
|
||||
cr_assert_neq(ret, 0);
|
||||
|
||||
/* Missing parts */
|
||||
ret = mapping_entry_parse_str(&m, "stats.owd");
|
||||
cr_assert_neq(ret, 0);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "data");
|
||||
cr_assert_neq(ret, 0);
|
||||
|
||||
/* This a type */
|
||||
ret = mapping_entry_parse_str(&m, "hdr.sequences");
|
||||
cr_assert_neq(ret, 0);
|
||||
|
||||
/* Check for superfluous chars at the end */
|
||||
ret = mapping_entry_parse_str(&m, "stats.ts.origin.bla");
|
||||
cr_assert_neq(ret, 0);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "stats.ts.origin.");
|
||||
cr_assert_neq(ret, 0);
|
||||
|
||||
ret = mapping_entry_parse_str(&m, "data[1-2]bla");
|
||||
cr_assert_neq(ret, 0);
|
||||
|
||||
/* Negative length of chunk */
|
||||
ret = mapping_entry_parse_str(&m, "data[5-3]");
|
||||
cr_assert_eq(ret, -1);
|
||||
}
|
||||
|
|
@ -34,7 +34,7 @@ ParameterizedTestParameters(pool, basic)
|
|||
ParameterizedTest(struct param *p, pool, basic)
|
||||
{
|
||||
int ret;
|
||||
struct pool pool;
|
||||
struct pool pool = { .state = STATE_DESTROYED };
|
||||
|
||||
void *ptr, *ptrs[p->pool_size];
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
|
||||
#define SIZE (1 << 10)
|
||||
|
||||
static struct queue q;
|
||||
static struct queue q = { .state = STATE_DESTROYED };
|
||||
|
||||
struct param {
|
||||
int volatile start;
|
||||
|
|
@ -61,7 +61,7 @@ __attribute__((always_inline)) static inline void nop()
|
|||
static void * producer(void *ctx)
|
||||
{
|
||||
int ret;
|
||||
struct param *p = (struct param *) ctx;
|
||||
struct param *p = ctx;
|
||||
|
||||
srand((unsigned) time(0) + thread_get_id());
|
||||
size_t nops = rand() % 1000;
|
||||
|
|
@ -97,7 +97,7 @@ static void * producer(void *ctx)
|
|||
static void * consumer(void *ctx)
|
||||
{
|
||||
int ret;
|
||||
struct param *p = (struct param *) ctx;
|
||||
struct param *p = ctx;
|
||||
|
||||
srand((unsigned) time(0) + thread_get_id());
|
||||
size_t nops = rand() % 1000;
|
||||
|
|
@ -136,7 +136,7 @@ static void * consumer(void *ctx)
|
|||
|
||||
void * producer_consumer(void *ctx)
|
||||
{
|
||||
struct param *p = (struct param *) ctx;
|
||||
struct param *p = ctx;
|
||||
|
||||
srand((unsigned) time(0) + thread_get_id());
|
||||
size_t nops = rand() % 1000;
|
||||
|
|
@ -168,7 +168,7 @@ void * producer_consumer(void *ctx)
|
|||
|
||||
void * producer_consumer_many(void *ctx)
|
||||
{
|
||||
struct param *p = (struct param *) ctx;
|
||||
struct param *p = ctx;
|
||||
|
||||
srand((unsigned) time(0) + thread_get_id());
|
||||
size_t nops = rand() % 1000;
|
||||
|
|
@ -284,7 +284,7 @@ ParameterizedTest(struct param *p, queue, multi_threaded, .timeout = 10)
|
|||
uint64_t start_tsc_time, end_tsc_time;
|
||||
|
||||
for (int i = 0; i < p->thread_count; ++i)
|
||||
pthread_create(&threads[i], NULL, p->thread_func, &p);
|
||||
pthread_create(&threads[i], NULL, p->thread_func, p);
|
||||
|
||||
sleep(1);
|
||||
|
||||
|
|
@ -300,18 +300,19 @@ ParameterizedTest(struct param *p, queue, multi_threaded, .timeout = 10)
|
|||
if (cycpop < 400)
|
||||
cr_log_info("cycles/op: %u\n", cycpop);
|
||||
else
|
||||
cr_log_warn("cycles/op are very high (%u). Are you running on a a hypervisor?\n", cycpop);
|
||||
cr_log_warn("cycles/op are very high (%u). Are you running on a hypervisor?\n", cycpop);
|
||||
|
||||
cr_assert_eq(queue_available(&q), 0);
|
||||
ret = queue_available(&q);
|
||||
cr_assert_eq(ret, 0);
|
||||
|
||||
ret = queue_destroy(&p->queue);
|
||||
cr_assert_eq(ret, 0, "Failed to create queue");
|
||||
cr_assert_eq(ret, 0, "Failed to destroy queue");
|
||||
}
|
||||
|
||||
Test(queue, init_destroy)
|
||||
{
|
||||
int ret;
|
||||
struct queue q;
|
||||
struct queue q = { .state = STATE_DESTROYED };
|
||||
|
||||
ret = queue_init(&q, 1024, &memtype_heap);
|
||||
cr_assert_eq(ret, 0); /* Should succeed */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue