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fpga/ips: add invalidate method to AxisCache and whitelist the IP in hwdef-parse.py

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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
This commit is contained in:
Niklas Eiling 2024-10-31 15:39:34 +01:00 • committed by Niklas Eiling
parent ce0959d4ba
commit a7427d7cc0
2 changed files with 11 additions and 1 deletions
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10
fpga/lib/ips/axis_cache.cpp
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@ -17,7 +17,10 @@ using namespace villas::fpga::ip;
AxisCache::AxisCache() : Node() {}
bool AxisCache::init() { return true; }
bool AxisCache::init() {
invalidate();
return true;
}
bool AxisCache::check() {
@ -47,6 +50,11 @@ bool AxisCache::check() {
return true;
}
void AxisCache::invalidate() {
setRegister(0, 1U << 31);
logger->info("invalidated AXIS cache.");
}
void AxisCache::setRegister(size_t reg, uint32_t value) {
if (reg >= registerNum) {
logger->error("Register index out of range: {}/{}", reg, registerNum);

2
tools/hwdef-parse.py
View file

@ -50,6 +50,7 @@ whitelist = [
["xilinx.com", "module_ref", "dinoif_dac"],
["xilinx.com", "module_ref", "axi_pcie_intc"],
["xilinx.com", "module_ref", "registerif"],
["xilinx.com", "module_ref", "axi_read_cache"],
["xilinx.com", "hls", "rtds2gpu"],
["xilinx.com", "hls", "mem"],
["acs.eonerc.rwth-aachen.de", "user", "axi_pcie_intc"],
@ -69,6 +70,7 @@ axi_converter_whitelist = [
["xilinx.com", "ip", "axis_register_slice"],
["xilinx.com", "ip", "axis_data_fifo"],
["xilinx.com", "ip", "floating_point"],
["xilinx.com", "module_ref", "prepend_seqnum"],
]
opponent = {