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fpga: add dinoif_adc to hwdef-parse.py
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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@ -47,6 +47,7 @@ whitelist = [
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["xilinx.com", "ip", "axi_iic"],
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["xilinx.com", "module_ref", "dinoif_fast"],
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["xilinx.com", "module_ref", "dinoif_fast_nologic"],
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["xilinx.com", "module_ref", "dinoif_adc"],
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["xilinx.com", "module_ref", "dinoif_dac"],
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["xilinx.com", "module_ref", "axi_pcie_intc"],
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["xilinx.com", "module_ref", "registerif"],
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