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fpga: add dinoif_adc to hwdef-parse.py

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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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Niklas Eiling 2024-11-15 13:21:47 +01:00 • committed by Niklas Eiling
parent 780dffb9ab
commit d905d16b74
1 changed files with 1 additions and 0 deletions
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tools/hwdef-parse.py
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@ -47,6 +47,7 @@ whitelist = [
["xilinx.com", "ip", "axi_iic"],
["xilinx.com", "module_ref", "dinoif_fast"],
["xilinx.com", "module_ref", "dinoif_fast_nologic"],
["xilinx.com", "module_ref", "dinoif_adc"],
["xilinx.com", "module_ref", "dinoif_dac"],
["xilinx.com", "module_ref", "axi_pcie_intc"],
["xilinx.com", "module_ref", "registerif"],