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updated RT-LAB project files

Browse source 
git-svn-id: https://zerberus.eonerc.rwth-aachen.de:8443/svn/s2ss/trunk@157 8ec27952-4edc-4aab-86aa-e87bb2611832
This commit is contained in:
Steffen Vogel 2014-07-14 17:58:48 +00:00
parent 604ce6724a
commit dad3ebecca
74 changed files with 45 additions and 23213 deletions
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21
clients/opal/models/AsyncIP_sl/AsyncIP_sl.llm
View file

@ -36,12 +36,17 @@ WATCHDOG_TIMEOUT=5000
INTERNAL_IGN_SOURCE_FILE=sfun_gen_async_ctrl.c sfun_recv_async.c sfun_send_async.c
INTERNAL_LIBRARY2=-lOpalAsyncApiR2011b
INTERNAL_LIBRARY3=-lOpalAsyncApiCore
[ExtraGetFilesComp]
AsyncIP=Binary
[ExtraPutFilesComp]
AsyncIP.c=Ascii
AsyncIP.mk=Ascii
AsyncIPUtils.h=Ascii
s2ss\AsyncIP.mk=Ascii
s2ss\include\Interface.h=Ascii
s2ss\include\MsgFormat.h=Ascii
s2ss\include\Sched.h=Ascii
s2ss\include\Socket.h=Ascii
s2ss\include\config.h=Ascii
s2ss\src\AsyncIP.c=Ascii
s2ss\src\Interface.c=Ascii
s2ss\src\Sched.c=Ascii
s2ss\src\Socket.c=Ascii
[ExtraPutFilesComp_1_RT_LAB]
C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalAsyncApiCore.a=Binary
[General]
@ -54,12 +59,12 @@ ATT_CREATED_ON=Thu Apr 15 08:21:54 1999
ATT_ENABLE_PTA=OFF
ATT_HANDLE_CONSOLE=ON
ATT_LAST_SAVED_BY=ACS
ATT_LAST_SAVED_ON=Wed May 28 12:53:21 2014
ATT_REVISION=1.425
ATT_LAST_SAVED_ON=Mon Jul 14 19:24:22 2014
ATT_REVISION=1.429
AutoRetrieveFiles=ON
AutoRetrieveRtlab=ON
CompilerVersion=AUTOMATIC
DESCRIPTION=Simple ping pong test between S2SS and OPAL$%CR%$$%CR%$Using sine waves no measure round trip time.
DESCRIPTION=Simple ping pong test between S2SS and OPAL$%CR%$$%CR%$Using sine waves to measure round trip time.
DinamoFlag=OFF
FILENAME=D:\msv\svo\s2ss\clients\opal\models\AsyncIP_sl\AsyncIP_sl.mdl
FORCE_RECOMPILE=0

78
clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl
View file

@ -7,7 +7,7 @@ Model {
NumRootInports 0
NumRootOutports 0
ParameterArgumentNames ""
ComputedModelVersion "1.426"
ComputedModelVersion "1.429"
NumModelReferences 0
NumTestPointedSignals 0
}
@ -28,9 +28,9 @@ Model {
ModifiedByFormat "%<Auto>"
LastModifiedBy "ACS"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Wed May 28 13:45:50 2014"
RTWModifiedTimeStamp 323183499
ModelVersionFormat "1.%<AutoIncrement:426>"
LastModifiedDate "Mon Jul 14 19:24:22 2014"
RTWModifiedTimeStamp 327266577
ModelVersionFormat "1.%<AutoIncrement:429>"
ConfigurationManager "none"
SampleTimeColors off
SampleTimeAnnotations off
@ -721,19 +721,6 @@ Model {
SignalType "auto"
SamplingMode "auto"
}
Block {
BlockType Sin
SineType "Time based"
TimeSource "Use simulation time"
Amplitude "1"
Bias "0"
Frequency "1"
Phase "0"
Samples "10"
Offset "0"
SampleTime "-1"
VectorParams1D on
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
@ -808,7 +795,7 @@ Model {
System {
Name "sc_console"
Location [2, 82, 1645, 997]
Open off
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
@ -1185,7 +1172,7 @@ Model {
}
Annotation {
Name "Simple analysis of round trip time"
Position [488, 57]
Position [293, 52]
FontName "Verdana"
FontSize 14
FontWeight "bold"
@ -1208,7 +1195,7 @@ Model {
MaskHideContents off
System {
Name "sm_ip_test"
Location [86, 258, 1746, 1156]
Location [2, 82, 1662, 980]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
@ -1220,13 +1207,13 @@ Model {
TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "183"
ZoomFactor "180"
Block {
BlockType Mux
Name "Mux"
SID "16"
Ports [3, 1]
Position [845, 125, 850, 175]
Position [870, 140, 875, 190]
ShowName off
Inputs "3"
DisplayOption "bar"
@ -1236,7 +1223,7 @@ Model {
Name "Mux1"
SID "17"
Ports [2, 1]
Position [255, 144, 260, 206]
Position [290, 209, 295, 271]
BackgroundColor "yellow"
ShowName off
Inputs "2"
@ -1247,13 +1234,13 @@ Model {
Name "OpIPSocketCtrl1"
SID "18"
Ports []
Position [15, 152, 144, 213]
Position [105, 112, 234, 173]
LibraryVersion "1.10"
SourceBlock "rtio_generic_ip/OpIPSocketCtrl"
SourceType "OpAsyncIPCtrl"
ctl_id "1"
proto "UDP/IP"
ip_addr_remote "137.226.160.91"
ip_addr_remote "134.130.169.31"
ip_port_remote "10200"
ip_port_local "10201"
ip_addr_mcast "0.0.0.0"
@ -1264,8 +1251,9 @@ Model {
Name "Pulse\nGenerator"
SID "44"
Ports [0, 1]
Position [165, 198, 215, 232]
Position [190, 238, 240, 272]
ZOrder -13
BackgroundColor "yellow"
PulseType "Time based"
Amplitude "5"
Period "0.1"
@ -1275,7 +1263,7 @@ Model {
BlockType Constant
Name "constants"
SID "19"
Position [165, 151, 235, 169]
Position [180, 216, 250, 234]
BackgroundColor "yellow"
NamePlacement "alternate"
Value "[1 2 3 4]"
@ -1285,7 +1273,7 @@ Model {
Name "data ready 1 kHz"
SID "20"
Ports [0, 1]
Position [265, 116, 310, 134]
Position [290, 131, 335, 149]
NamePlacement "alternate"
SampleTime "0.001"
}
@ -1294,7 +1282,7 @@ Model {
Name "receive message 1"
SID "21"
Ports [1, 3]
Position [600, 144, 775, 186]
Position [625, 159, 800, 201]
LibraryVersion "1.348"
SourceBlock "rtlab/Communication/Asynchronous/OpAsyncRecv"
SourceType "OpAsyncRecv"
@ -1317,7 +1305,7 @@ Model {
Name "send message 1"
SID "22"
Ports [2, 1]
Position [350, 114, 520, 156]
Position [375, 129, 545, 171]
LibraryVersion "1.348"
SourceBlock "rtlab/Communication/Asynchronous/OpAsyncSend"
SourceType "OpAsyncSend"
@ -1340,31 +1328,21 @@ Model {
BlockType SignalSpecification
Name "set width"
SID "23"
Position [805, 172, 830, 188]
Position [830, 187, 855, 203]
Dimensions "5"
}
Block {
BlockType Sin
Name "sine"
SID "24"
Ports [0, 1]
Position [65, 37, 135, 73]
BackgroundColor "yellow"
Amplitude "1.5"
Frequency "50"
}
Block {
BlockType Constant
Name "timeout"
SID "25"
Position [555, 158, 585, 172]
Position [580, 173, 610, 187]
Value "2"
}
Block {
BlockType Outport
Name "data recv"
SID "26"
Position [890, 172, 925, 188]
Position [915, 187, 950, 203]
BackgroundColor "yellow"
IconDisplay "Port number"
}
@ -1372,9 +1350,8 @@ Model {
BlockType Outport
Name "errors_status"
SID "27"
Position [890, 142, 925, 158]
Position [915, 142, 950, 158]
BackgroundColor "yellow"
NamePlacement "alternate"
Port "2"
IconDisplay "Port number"
}
@ -1382,7 +1359,7 @@ Model {
BlockType Outport
Name "data send"
SID "28"
Position [890, 217, 925, 233]
Position [915, 232, 950, 248]
BackgroundColor "yellow"
Port "3"
IconDisplay "Port number"
@ -1420,6 +1397,7 @@ Model {
Line {
SrcBlock "Mux"
SrcPort 1
Points [0, -15]
DstBlock "errors_status"
DstPort 1
}
@ -1439,15 +1417,14 @@ Model {
Labels [0, 0]
SrcBlock "Mux1"
SrcPort 1
Points [55, 0]
Points [45, 0]
Branch {
Points [0, -30]
Points [0, -80]
DstBlock "send message 1"
DstPort 2
}
Branch {
Labels [1, 0]
Points [0, 50]
DstBlock "data send"
DstPort 1
}
@ -1461,13 +1438,12 @@ Model {
Line {
SrcBlock "Pulse\nGenerator"
SrcPort 1
Points [0, -25]
DstBlock "Mux1"
DstPort 2
}
Annotation {
Name "Simple S2SS to OPAL test using UDP messages"
Position [433, 47]
Position [288, 52]
FontName "Verdana"
FontSize 14
FontWeight "bold"

1226
clients/opal/models/AsyncIP_sl/AsyncIP_sl.mdl.r2006b
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File diff suppressed because it is too large Load diff

BIN
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/AsyncIP
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154
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/OpalSnapshotUtil.c
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@ -1,154 +0,0 @@
/**
* This function is generated by RT-LAB during model compilation (at 'generation' step).
* This function copies data from src to dst, ignoring pointers.
* Note that only PWork are supposed to be pointers within a DWork structure
* and that sub-structures are copied in one operation since they do not contain pointers.
*/
int OpalSnapshot_Copy_DWork(void * src, void * dst) {
D_Work * pSrc = (D_Work*)src;
D_Work * pDst = (D_Work*)dst;
int size = 0, eltSize = 0;
eltSize = sizeof(pSrc->SFunction_PreviousInput);
memcpy(&pDst->SFunction_PreviousInput, &pSrc->SFunction_PreviousInput, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->clockTickCounter);
memcpy(&pDst->clockTickCounter, &pSrc->clockTickCounter, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->clockTickCounter_c);
memcpy(&pDst->clockTickCounter_c, &pSrc->clockTickCounter_c, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->SFunction_IWORK);
memcpy(&pDst->SFunction_IWORK, &pSrc->SFunction_IWORK, eltSize);
size += eltSize;
return size;
}
/**
* This function is generated by RT-LAB during model compilation (at 'generation' step).
* This function copies data from a raw buffer (src)
* to an RT_MODEL structure(dst), ignoring pointers.
* Note that sub-structures are copied in one operation since they cannot contain pointers.
*/
int OpalSnapshot_Copy_TimingData(void * src, void * dst) {
RT_MODEL tmpBuffer;
RT_MODEL * pSrc = &tmpBuffer;
RT_MODEL * pDst = (RT_MODEL *)dst;
int TimingSize = sizeof(tmpBuffer.Timing);
int size = 0, eltSize = 0;
memcpy(&tmpBuffer.Timing, src, TimingSize);
eltSize = sizeof(pSrc->Timing.clockTick0);
memcpy(&pDst->Timing.clockTick0, &pSrc->Timing.clockTick0, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.clockTick1);
memcpy(&pDst->Timing.clockTick1, &pSrc->Timing.clockTick1, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.clockTickH0);
memcpy(&pDst->Timing.clockTickH0, &pSrc->Timing.clockTickH0, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.clockTickH1);
memcpy(&pDst->Timing.clockTickH1, &pSrc->Timing.clockTickH1, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.tFinal);
memcpy(&pDst->Timing.tFinal, &pSrc->Timing.tFinal, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.offsetTimesArray);
memcpy(&pDst->Timing.offsetTimesArray, &pSrc->Timing.offsetTimesArray, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.perTaskSampleHitsArray);
memcpy(&pDst->Timing.perTaskSampleHitsArray, &pSrc->Timing.perTaskSampleHitsArray, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.sampleHitArray);
memcpy(&pDst->Timing.sampleHitArray, &pSrc->Timing.sampleHitArray, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.sampleTimesArray);
memcpy(&pDst->Timing.sampleTimesArray, &pSrc->Timing.sampleTimesArray, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.sampleTimeTaskIDArray);
memcpy(&pDst->Timing.sampleTimeTaskIDArray, &pSrc->Timing.sampleTimeTaskIDArray, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.simTimeStep);
memcpy(&pDst->Timing.simTimeStep, &pSrc->Timing.simTimeStep, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.tStart);
memcpy(&pDst->Timing.tStart, &pSrc->Timing.tStart, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.stepSize);
memcpy(&pDst->Timing.stepSize, &pSrc->Timing.stepSize, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.stepSize0);
memcpy(&pDst->Timing.stepSize0, &pSrc->Timing.stepSize0, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.stepSize1);
memcpy(&pDst->Timing.stepSize1, &pSrc->Timing.stepSize1, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.stopRequestedFlag);
memcpy(&pDst->Timing.stopRequestedFlag, &pSrc->Timing.stopRequestedFlag, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.TaskCounters);
memcpy(&pDst->Timing.TaskCounters, &pSrc->Timing.TaskCounters, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.tArray);
memcpy(&pDst->Timing.tArray, &pSrc->Timing.tArray, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->Timing.timeOfLastOutput);
memcpy(&pDst->Timing.timeOfLastOutput, &pSrc->Timing.timeOfLastOutput, eltSize);
size += eltSize;
return size;
}
/**
* This function is generated by RT-LAB during model compilation (at 'generation' step).
* This function copies data from a raw buffer (src)
* to an RT_MODEL structure(dst), ignoring pointers.
* Note that ingData must not be copied since it contains pointers.
*/
int OpalSnapshot_Copy_ModelData(void * src, void * dst) {
RT_MODEL tmpBuffer;
RT_MODEL * pSrc = &tmpBuffer;
RT_MODEL * pDst = (RT_MODEL *)dst;
int ModelDataSize = sizeof(tmpBuffer.ModelData);
int size = 0, eltSize = 0;
memcpy(&tmpBuffer.ModelData, src, ModelDataSize);
eltSize = sizeof(pSrc->ModelData.blkStateChange);
memcpy(&pDst->ModelData.blkStateChange, &pSrc->ModelData.blkStateChange, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->ModelData.derivCacheNeedsReset);
memcpy(&pDst->ModelData.derivCacheNeedsReset, &pSrc->ModelData.derivCacheNeedsReset, eltSize);
size += eltSize;
eltSize = sizeof(pSrc->ModelData.zCCacheNeedsReset);
memcpy(&pDst->ModelData.zCCacheNeedsReset, &pSrc->ModelData.zCCacheNeedsReset, eltSize);
size += eltSize;
return size;
}

BIN
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test
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2
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.bat
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@ -1,2 +0,0 @@
set MATLAB=C:\Program Files (x86)\MATLAB\R2011b
make -f asyncip_sl_1_sm_ip_test.mk GENERATE_REPORT=0 EXT_MODE=0 EXTMODE_STATIC_ALLOC=0 TMW_EXTMODE_TESTING=0 EXTMODE_STATIC_ALLOC_SIZE=1000000 EXTMODE_TRANSPORT=0

1170
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.c
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File diff suppressed because it is too large Load diff

1371
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.h
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61
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.log
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@ -1,61 +0,0 @@
--------------- Transferring files ... ------------------------------
Transferring in binary mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test ... OK.
--------------- Done transferring files -----------------------------
Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_preload.py ... done
Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_subsys_preload.py ... done
Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
12 CPUs active on this Computer
libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
Highest active CPU: 12
Subsystem sm_ip_test allocates 1 cores.
model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
Monitoring is enabled
RECV: connection to host established
SEND: connection to host established
Display of standard output will be disabled
AsyncIP: Version : Opal-RT_20060524
AsyncIP: Protocol : UDP/IP
AsyncIP: Remote Address : 137.226.160.91
AsyncIP: Remote Port : 10200
AsyncIP: Local Port : 10201
AsyncIP: SendToIPPort thread started
AsyncIP: RecvFromIPPort thread started
SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
Synchronized with software timer.
Real-time SingleTasking mode.
RT-LAB license ok. Unlimited time license.
Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
[0]: PAUSE mode, IO set to pause value.
Total of 0 Overrun detected.
Wed May 28 12:54:01 2014
Starting transfer of /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/opasyncip_sl_sm_ip_test_0.snap...
Transfer of /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/opasyncip_sl_sm_ip_test_0.snap OK
[1]: RUN mode, IO set to run value.
Synchronized step size = 50 us.
Wed May 28 12:54:24 2014
Main priority set to 99
AsyncIP: SendToIPPort: Finished
[17891814]: Reset
Total of 0 Overrun detected.
Wed May 28 13:09:18 2014
AsyncIP: RecvFromIPPort: Finished
Reset done
Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_postreset.py ... done
Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_subsys_postreset.py ... done
--------------- Retrieving files ... ---------------------------------
Setting local directory to D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\asyncip_sl_sm_ip_test\OpREDHAWKtarget\... OK.
Transferring in ascii mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/asyncip_sl_1_sm_ip_test_147_125401.log ... OK.
Transferring in ascii mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/target_report.xml ... OK.
--------------- Done retrieving files --------------------------------

156
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.map
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@ -1,156 +0,0 @@
[Parameter]
0=asyncip_sl_1_sm_ip_test/OpCCode_do_not_touch/S-Function1|Value|0|Scalar|1|1|0.0|Constant|
1=asyncip_sl_1_sm_ip_test/OpCCode_do_not_touch/S-Function|X0|0|Scalar|1|1|0.0|Memory|
2=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|Amplitude|1|Scalar|1|1|1.0|DiscretePulseGenerator|
3=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|Period|2|Scalar|1|1|2.0|DiscretePulseGenerator|
4=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|PulseWidth|1|Scalar|1|1|1.0|DiscretePulseGenerator|
5=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|PhaseDelay|0|Scalar|1|1|0.0|DiscretePulseGenerator|
6=asyncip_sl_1_sm_ip_test/sm_ip_test/constants|Value|[1 2 3 4]|RVector|1|4|1.0|2.0|3.0|4.0|Constant|
7=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|Amplitude|5|Scalar|1|1|5.0|DiscretePulseGenerator|
8=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|Period| |Scalar|1|1|2000.0|DiscretePulseGenerator|
9=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|PulseWidth| |Scalar|1|1|600.0|DiscretePulseGenerator|
10=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|PhaseDelay|0|Scalar|1|1|0.0|DiscretePulseGenerator|
11=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P1Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
12=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P1|ctl_id|Scalar|1|1|1.0|S-Function sfun_send_async|
13=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P2Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
14=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P2|send_id|Scalar|1|1|1.0|S-Function sfun_send_async|
15=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P3Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
16=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P3|mode|Scalar|1|1|3.0|S-Function sfun_send_async|
17=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P4Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
18=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P4|fp1|Scalar|1|1|1.0|S-Function sfun_send_async|
19=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P5Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
20=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P5|fp2|Scalar|1|1|2.0|S-Function sfun_send_async|
21=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P6Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
22=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P6|fp3|Scalar|1|1|3.0|S-Function sfun_send_async|
23=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P7Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
24=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P7|fp4|Scalar|1|1|4.0|S-Function sfun_send_async|
25=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P8Size| |RVector|1|2|1.0|1.0|S-Function sfun_send_async|
26=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P8|fp5|Scalar|1|1|5.0|S-Function sfun_send_async|
27=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P9Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
28=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P9| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|49.0|S-Function sfun_send_async|
29=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P10Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
30=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P10| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|50.0|S-Function sfun_send_async|
31=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P11Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
32=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P11| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|51.0|S-Function sfun_send_async|
33=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P12Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
34=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P12| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|52.0|S-Function sfun_send_async|
35=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P13Size| |RVector|1|2|1.0|7.0|S-Function sfun_send_async|
36=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|P13| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|53.0|S-Function sfun_send_async|
37=asyncip_sl_1_sm_ip_test/sm_ip_test/timeout|Value|2|Scalar|1|1|2.0|Constant|
38=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P1Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
39=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P1|ctl_id|Scalar|1|1|1.0|S-Function sfun_recv_async|
40=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P2Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
41=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P2|recv_id|Scalar|1|1|1.0|S-Function sfun_recv_async|
42=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P3Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
43=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P3|fp1|Scalar|1|1|1.0|S-Function sfun_recv_async|
44=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P4Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
45=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P4|fp2|Scalar|1|1|2.0|S-Function sfun_recv_async|
46=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P5Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
47=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P5|fp3|Scalar|1|1|3.0|S-Function sfun_recv_async|
48=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P6Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
49=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P6|fp4|Scalar|1|1|4.0|S-Function sfun_recv_async|
50=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P7Size| |RVector|1|2|1.0|1.0|S-Function sfun_recv_async|
51=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P7|fp5|Scalar|1|1|5.0|S-Function sfun_recv_async|
52=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P8Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
53=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P8| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|49.0|S-Function sfun_recv_async|
54=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P9Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
55=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P9| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|50.0|S-Function sfun_recv_async|
56=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P10Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
57=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P10| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|51.0|S-Function sfun_recv_async|
58=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P11Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
59=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P11| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|52.0|S-Function sfun_recv_async|
60=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P12Size| |RVector|1|2|1.0|7.0|S-Function sfun_recv_async|
61=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|P12| |RVector|1|7|115.0|116.0|114.0|105.0|110.0|103.0|53.0|S-Function sfun_recv_async|
62=asyncip_sl_1_sm_ip_test/sm_ip_test/rtlab_send_subsystem/Subsystem1/Send1/S-Function|P1Size| |RVector|1|2|1.0|1.0|S-Function OP_SEND|
63=asyncip_sl_1_sm_ip_test/sm_ip_test/rtlab_send_subsystem/Subsystem1/Send1/S-Function|P1|Acqu_group|Scalar|1|1|1.0|S-Function OP_SEND|
64=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P1Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
65=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P1|ctl_id|Scalar|1|1|1.0|S-Function sfun_gen_async_ctrl|
66=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P2Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
67=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P2|proto|Scalar|1|1|1.0|S-Function sfun_gen_async_ctrl|
68=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P3Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
69=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P3|ip_port_remote|Scalar|1|1|10200.0|S-Function sfun_gen_async_ctrl|
70=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P4Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
71=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P4|ip_port_local|Scalar|1|1|10201.0|S-Function sfun_gen_async_ctrl|
72=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P5Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
73=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P5|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
74=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P6Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
75=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P6|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
76=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P7Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
77=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P7|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
78=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P8Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
79=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P8|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
80=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P9Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
81=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P9|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
82=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P10Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
83=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P10|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
84=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P11Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
85=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P11|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
86=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P12Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
87=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P12|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
88=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P13Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
89=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P13|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
90=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P14Size| |RVector|1|2|1.0|14.0|S-Function sfun_gen_async_ctrl|
91=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P14| |RVector|1|14|49.0|51.0|55.0|46.0|50.0|50.0|54.0|46.0|49.0|54.0|48.0|46.0|57.0|49.0|S-Function sfun_gen_async_ctrl|
92=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P15Size| |RVector|1|2|1.0|7.0|S-Function sfun_gen_async_ctrl|
93=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P15| |RVector|1|7|48.0|46.0|48.0|46.0|48.0|46.0|48.0|S-Function sfun_gen_async_ctrl|
94=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P16Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
95=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P17Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
96=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P18Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
97=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P19Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
98=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P20Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
99=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P21Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
100=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P22Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
101=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P23Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
102=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P24Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
103=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P25Size| |RVector|1|2|0.0|0.0|S-Function sfun_gen_async_ctrl|
104=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P26Size| |RVector|1|2|1.0|7.0|S-Function sfun_gen_async_ctrl|
105=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P26| |RVector|1|7|65.0|115.0|121.0|110.0|99.0|73.0|80.0|S-Function sfun_gen_async_ctrl|
106=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P27Size| |RVector|1|2|1.0|1.0|S-Function sfun_gen_async_ctrl|
107=asyncip_sl_1_sm_ip_test/sm_ip_test/OpIPSocketCtrl1|P27|0|Scalar|1|1|0.0|S-Function sfun_gen_async_ctrl|
nbParameters=108
[Signal]
0=asyncip_sl_1_sm_ip_test/OpCCode_do_not_touch/S-Function|NULL|0|1|1|1|S|Memory|
1=asyncip_sl_1_sm_ip_test/OpCCode_do_not_touch/Sum|NULL|1|1|1|1|S|Sum|
2=asyncip_sl_1_sm_ip_test/sm_ip_test/data ready 1 kHz|NULL|2|1|1|1|S|DiscretePulseGenerator|
3=asyncip_sl_1_sm_ip_test/sm_ip_test/Pulse Generator|NULL|3|1|1|1|S|DiscretePulseGenerator|
4=asyncip_sl_1_sm_ip_test/sm_ip_test/send message 1/S-Function2|NULL|4|1|1|1|S|S-Function sfun_send_async|
5=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|NULL|5|1|1|1|S|S-Function sfun_recv_async|
6=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|NULL|6|1|1|1|S|S-Function sfun_recv_async|
7=asyncip_sl_1_sm_ip_test/sm_ip_test/receive message 1/S-Function1|NULL|7|5|5|1|V|S-Function sfun_recv_async|
nbSignals=8
[ModelDataStructure]
0=blkStateChange
27=derivCacheNeedsReset
137=zCCacheNeedsReset
[dwork]
0=SFunction_PreviousInput|real_T|
4=clockTickCounter|int32_T|
5=clockTickCounter_c|int32_T|
6=SFunction_IWORK|IWORK|
[TimingStructure]
4=clockTick0
5=clockTick1
6=clockTickH0
7=clockTickH1
32=tFinal
74=offsetTimesArray
80=perTaskSampleHitsArray
96=sampleHitArray
100=sampleTimesArray
103=sampleTimeTaskIDArray
106=simTimeStep
108=tStart
109=stepSize
110=stepSize0
111=stepSize1
114=stopRequestedFlag
121=TaskCounters
125=tArray
139=timeOfLastOutput
[dummy]

637
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.mk
View file

@ -1,637 +0,0 @@
# File : TARGET.tmf
#
# $Revision 1.1 $
#
# Abstract:
# Real-Time Workshop template makefile for building a Neutrino-based
# stand-alone real-time version of SIMULINK model using
# generated C code.
#
# Note that this template is automatically customized by the Real-Time
# Workshop build procedure to create "<model>.mk"
#
# The following defines can be used to modify the behavior of the
# build:
# OPTS - User specific compile options, such as
# OPTS=-DMULTITASKING to enable multitasking mode.
# OPT_OPTS - Optimization options. Default is -Oatx. To enable
# debugging define DEBUG.
# USER_SRCS - Additional user sources, such as files needed by
# S-functions.
# USER_INCS - Additional include paths
# (i.e. USER_INCS="-Iwhere-ever -Iwhere-ever2")
#------------------------ Macros read by make_rtw -----------------------------
#
# The following macros are read by the Real-Time Workshop build procedure:
#
# MAKE - This is the command used to invoke the make utility
# HOST - What platform this template makefile is targeted for
# (i.e. PC or UNIX)
# BUILD - Invoke make from the Real-Time Workshop build procedure
# (yes/no)?
# SYS_TARGET_FILE - Name of system target file.
MAKE = make
HOST = PC
BUILD = no
SYS_TARGET_FILE = rtlab_rtmodel.tlc
#---------------------- Tokens expanded by make_rtw ---------------------------
#
# The following tokens, when wrapped with "|>" and "|<" are expanded by the
# Real-Time Workshop build procedure.
#
# MODEL_NAME - Name of the SIMULINK block diagram
# MODEL_MODULES - Any additional generated source modules
# MAKEFILE_NAME - Name of makefile created from template makefile <model>.mk
# MATLAB_ROOT - Path to were MATLAB is installed.
# S_FUNCTIONS - List of S-functions.
# SOLVER - Solver source file name
# NUMST - Number of sample times
# TID01EQ - yes (1) or no (0): Are sampling rates of continuous task
# (tid=0) and 1st discrete task equal.
# NCSTATES - Number of continuous states
# COMPUTER - Computer type. See the MATLAB computer command.
# BUILDARGS - Options passed in at the command line.
MODEL = asyncip_sl_1_sm_ip_test
MODULES = asyncip_sl_1_sm_ip_test_data.c rtGetInf.c rtGetNaN.c rt_logging.c rt_matrx.c rt_nonfinite.c rt_printf.c
MAKEFILE = asyncip_sl_1_sm_ip_test.mk
MATLAB_ROOT = C:\Program Files (x86)\MATLAB\R2011b
ALT_MATLAB_ROOT = C:\PROGRA~2\MATLAB\R2011b
S_FUNCTIONS = sfun_send_async.c sfun_recv_async.c OP_SEND.c sfun_gen_async_ctrl.c
SOLVER =
NUMST = 2
TID01EQ = 0
NCSTATES = 0
COMPUTER = PCWIN
BUILDARGS = GENERATE_REPORT=0 EXT_MODE=0 EXTMODE_STATIC_ALLOC=0 TMW_EXTMODE_TESTING=0 EXTMODE_STATIC_ALLOC_SIZE=1000000 EXTMODE_TRANSPORT=0
MULTITASKING = 0
MODELREFS =
MODELLIB = asyncip_sl_1_sm_ip_testlib.lib
MODELREF_LINK_LIBS =
MODELREF_LINK_RSPFILE = asyncip_sl_1_sm_ip_test_ref.rsp
MODELREF_INC_PATH =
RELATIVE_PATH_TO_ANCHOR = ..
MODELREF_TARGET_TYPE = NONE
SHARED_SRC =
SHARED_SRC_DIR =
SHARED_BIN_DIR =
SHARED_LIB =
# SHARED_BIN_DIR = unused
# SHARED_LIB = unused
UNAME = $(shell uname)
ifeq "$(UNAME)" "QNX" ##### nto
ifeq ($(MODELREF_TARGET_TYPE), NONE)
SHARED_SRC := _sharedutils\*.c*
SHARED_SRC_DIR := _sharedutils
RELATIVE_PATH_TO_ANCHOR :=
MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS:.lib=.a)
MODELLIB := $(MODELLIB:.lib=.a)
else
SHARED_SRC := ..\_sharedutils\*.c*
SHARED_SRC_DIR := ..\_sharedutils
RELATIVE_PATH_TO_ANCHOR := ..
MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS:.lib=.a)
MODELLIB := $(MODELLIB:.lib=.a)
endif
else
ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
ifeq ($(MODELREF_TARGET_TYPE), NONE)
SHARED_SRC := _sharedutils\*.c*
SHARED_SRC_DIR := _sharedutils
RELATIVE_PATH_TO_ANCHOR :=
MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS:.lib=.a)
MODELLIB := $(MODELLIB:.lib=.a)
else
SHARED_SRC := ..\_sharedutils\*.c*
SHARED_SRC_DIR := ..\_sharedutils
RELATIVE_PATH_TO_ANCHOR := ..
MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS:.lib=.a)
MODELLIB := $(MODELLIB:.lib=.a)
endif
else
ifeq ($(MODELREF_TARGET_TYPE), NONE)
SHARED_SRC := $(SHARED_SRC)
SHARED_SRC_DIR := $(SHARED_SRC_DIR)
RELATIVE_PATH_TO_ANCHOR := $(RELATIVE_PATH_TO_ANCHOR)
MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS)
MODELLIB := $(MODELLIB)
else
SHARED_SRC := $(SHARED_SRC)
SHARED_SRC_DIR := $(SHARED_SRC_DIR)
RELATIVE_PATH_TO_ANCHOR := $(RELATIVE_PATH_TO_ANCHOR)
MODELREF_LINK_LIBS := $(MODELREF_LINK_LIBS)
MODELLIB := $(MODELLIB)
endif
endif
endif
#----------------------------- Source Files ------------------------------
MOD_TMP1 = $(MODULES:blms_an_wn_cc_rt.c= )
MOD_TMP2 = $(MOD_TMP1:blms_an_wn_dd_rt.c= )
MOD_TMP3 = $(MOD_TMP2:blms_an_wn_rr_rt.c= )
MOD_TMP4 = $(MOD_TMP3:blms_an_wn_zz_rt.c= )
MOD_TMP5 = $(MOD_TMP4:blms_an_wy_cc_rt.c= )
MOD_TMP6 = $(MOD_TMP5:blms_an_wy_dd_rt.c= )
MOD_TMP7 = $(MOD_TMP6:blms_an_wy_rr_rt.c= )
MOD_TMP8 = $(MOD_TMP7:blms_an_wy_zz_rt.c= )
MOD_TMP9 = $(MOD_TMP8:blms_ay_wn_cc_rt.c= )
MOD_TMP10 = $(MOD_TMP9:blms_ay_wn_dd_rt.c= )
MOD_TMP11 = $(MOD_TMP10:blms_ay_wn_rr_rt.c= )
MOD_TMP12 = $(MOD_TMP11:blms_ay_wn_zz_rt.c= )
MOD_TMP13 = $(MOD_TMP12:blms_ay_wy_cc_rt.c= )
MOD_TMP14 = $(MOD_TMP13:blms_ay_wy_dd_rt.c= )
MOD_TMP15 = $(MOD_TMP14:blms_ay_wy_rr_rt.c= )
MOD_TMP16 = $(MOD_TMP15:blms_ay_wy_zz_rt.c= )
MOD_TMP17 = $(MOD_TMP16:is_little_endian_rt.c= )
MOD_TMP18 = $(MOD_TMP17:eph_zc_fcn_rt.c= )
MOD_TMP19 = $(MOD_TMP18:2chabank_fr_df_cc_rt.c= )
MOD_TMP20 = $(MOD_TMP19:2chabank_fr_df_cr_rt.c= )
MOD_TMP21 = $(MOD_TMP20:2chabank_fr_df_dd_rt.c= )
MOD_TMP22 = $(MOD_TMP21:2chabank_fr_df_rr_rt.c= )
MOD_TMP23 = $(MOD_TMP22:2chabank_fr_df_zd_rt.c= )
MOD_TMP24 = $(MOD_TMP23:2chabank_fr_df_zz_rt.c= )
MOD_TMP25 = $(MOD_TMP24:2chsbank_df_cc_rt.c= )
MOD_TMP26 = $(MOD_TMP25:2chsbank_df_cr_rt.c= )
MOD_TMP27 = $(MOD_TMP26:2chsbank_df_dd_rt.c= )
MOD_TMP28 = $(MOD_TMP27:2chsbank_df_rr_rt.c= )
MOD_TMP29 = $(MOD_TMP28:2chsbank_df_zd_rt.c= )
MOD_TMP30 = $(MOD_TMP29:2chsbank_df_zz_rt.c= )
MOD_TMP31 = $(MOD_TMP30:ic_copy_channel_rt.c= )
MOD_TMP32 = $(MOD_TMP31:ic_copy_matrix_rt.c= )
MOD_TMP33 = $(MOD_TMP32:ic_copy_scalar_rt.c= )
MOD_TMP34 = $(MOD_TMP33:ic_copy_vector_rt.c= )
MOD_TMP35 = $(MOD_TMP34:ic_old_copy_fcns_rt.c= )
MOD_TMP36 = $(MOD_TMP35:mmpcmaudio_rt.c= )
MOD_TMP37 = $(MOD_TMP36:mmrgb24convert2gray_rt.c= )
MOD_TMP38 = $(MOD_TMP37:mmrgb24convert_rt.c= )
MOD_TMP39 = $(MOD_TMP38:mmrgb24output_rt.c= )
MOD_TMP40 = $(MOD_TMP39:mmrgb24paddedoutput_rt.c= )
MOD_TMP41 = $(MOD_TMP40:polyval_cc_rt.c= )
MOD_TMP42 = $(MOD_TMP41:polyval_cr_rt.c= )
MOD_TMP43 = $(MOD_TMP42:polyval_dd_rt.c= )
MOD_TMP44 = $(MOD_TMP43:polyval_dz_rt.c= )
MOD_TMP45 = $(MOD_TMP44:polyval_rc_rt.c= )
MOD_TMP46 = $(MOD_TMP45:polyval_rr_rt.c= )
MOD_TMP47 = $(MOD_TMP46:polyval_zd_rt.c= )
MOD_TMP48 = $(MOD_TMP47:polyval_zz_rt.c= )
MOD_TMP49 = $(MOD_TMP48:sort_ins_idx_d_rt.c= )
MOD_TMP50 = $(MOD_TMP49:sort_ins_idx_r_rt.c= )
MOD_TMP51 = $(MOD_TMP50:sort_ins_idx_s08_rt.c= )
MOD_TMP52 = $(MOD_TMP51:sort_ins_idx_s16_rt.c= )
MOD_TMP53 = $(MOD_TMP52:sort_ins_idx_s32_rt.c= )
MOD_TMP54 = $(MOD_TMP53:sort_ins_idx_u08_rt.c= )
MOD_TMP55 = $(MOD_TMP54:sort_ins_idx_u16_rt.c= )
MOD_TMP56 = $(MOD_TMP55:sort_ins_idx_u32_rt.c= )
MOD_TMP57 = $(MOD_TMP56:sort_ins_val_d_rt.c= )
MOD_TMP58 = $(MOD_TMP57:sort_ins_val_r_rt.c= )
MOD_TMP59 = $(MOD_TMP58:sort_ins_val_s08_rt.c= )
MOD_TMP60 = $(MOD_TMP59:sort_ins_val_s16_rt.c= )
MOD_TMP61 = $(MOD_TMP60:sort_ins_val_s32_rt.c= )
MOD_TMP62 = $(MOD_TMP61:sort_ins_val_u08_rt.c= )
MOD_TMP63 = $(MOD_TMP62:sort_ins_val_u16_rt.c= )
MOD_TMP64 = $(MOD_TMP63:sort_ins_val_u32_rt.c= )
MOD_TMP65 = $(MOD_TMP64:sort_qk_idx_d_rt.c= )
MOD_TMP66 = $(MOD_TMP65:sort_qk_idx_r_rt.c= )
MOD_TMP67 = $(MOD_TMP66:sort_qk_idx_s08_rt.c= )
MOD_TMP68 = $(MOD_TMP67:sort_qk_idx_s16_rt.c= )
MOD_TMP69 = $(MOD_TMP68:sort_qk_idx_s32_rt.c= )
MOD_TMP70 = $(MOD_TMP69:sort_qk_idx_u08_rt.c= )
MOD_TMP71 = $(MOD_TMP70:sort_qk_idx_u16_rt.c= )
MOD_TMP72 = $(MOD_TMP71:sort_qk_idx_u32_rt.c= )
MOD_TMP73 = $(MOD_TMP72:sort_qk_val_d_rt.c= )
MOD_TMP74 = $(MOD_TMP73:sort_qk_val_r_rt.c= )
MOD_TMP75 = $(MOD_TMP74:sort_qk_val_s08_rt.c= )
MOD_TMP76 = $(MOD_TMP75:sort_qk_val_s16_rt.c= )
MOD_TMP77 = $(MOD_TMP76:sort_qk_val_s32_rt.c= )
MOD_TMP78 = $(MOD_TMP77:sort_qk_val_u08_rt.c= )
MOD_TMP79 = $(MOD_TMP78:sort_qk_val_u16_rt.c= )
MOD_TMP80 = $(MOD_TMP79:sort_qk_val_u32_rt.c= )
MOD_TMP81 = $(MOD_TMP80:srt_qid_findpivot_d_rt.c= )
MOD_TMP82 = $(MOD_TMP81:srt_qid_findpivot_r_rt.c= )
MOD_TMP83 = $(MOD_TMP82:srt_qid_partition_d_rt.c= )
MOD_TMP84 = $(MOD_TMP83:srt_qid_partition_r_rt.c= )
MOD_TMP85 = $(MOD_TMP84:srt_qkrec_c_rt.c= )
MOD_TMP86 = $(MOD_TMP85:srt_qkrec_d_rt.c= )
MOD_TMP87 = $(MOD_TMP86:srt_qkrec_r_rt.c= )
MOD_TMP88 = $(MOD_TMP87:srt_qkrec_z_rt.c= )
MOD_TMP89 = $(MOD_TMP88:randsrccreateseeds_32_rt.c= )
MOD_TMP90 = $(MOD_TMP89:randsrccreateseeds_64_rt.c= )
MOD_TMP91 = $(MOD_TMP90:randsrcinitstate_gc_32_rt.c= )
MOD_TMP92 = $(MOD_TMP91:randsrcinitstate_gc_64_rt.c= )
MOD_TMP93 = $(MOD_TMP92:randsrcinitstate_gz_rt.c= )
MOD_TMP94 = $(MOD_TMP93:randsrcinitstate_u_32_rt.c= )
MOD_TMP95 = $(MOD_TMP94:randsrcinitstate_u_64_rt.c= )
MOD_TMP96 = $(MOD_TMP95:randsrc_gc_c_rt.c= )
MOD_TMP97 = $(MOD_TMP96:randsrc_gc_d_rt.c= )
MOD_TMP98 = $(MOD_TMP97:randsrc_gc_r_rt.c= )
MOD_TMP99 = $(MOD_TMP98:randsrc_gc_z_rt.c= )
MOD_TMP100 = $(MOD_TMP99:randsrc_gz_c_rt.c= )
MOD_TMP101 = $(MOD_TMP100:randsrc_gz_d_rt.c= )
MOD_TMP102 = $(MOD_TMP101:randsrc_gz_r_rt.c= )
MOD_TMP103 = $(MOD_TMP102:randsrc_gz_z_rt.c= )
MOD_TMP104 = $(MOD_TMP103:randsrc_u_c_rt.c= )
MOD_TMP105 = $(MOD_TMP104:randsrc_u_d_rt.c= )
MOD_TMP106 = $(MOD_TMP105:randsrc_u_r_rt.c= )
MOD_TMP107 = $(MOD_TMP106:randsrc_u_z_rt.c= )
MOD_TMP108 = $(MOD_TMP107:buf_copy_frame_to_mem_OL_1ch_rt.c= )
MOD_TMP109 = $(MOD_TMP108:buf_copy_frame_to_mem_OL_rt.c= )
MOD_TMP110 = $(MOD_TMP109:buf_copy_input_to_output_1ch_rt.c= )
MOD_TMP111 = $(MOD_TMP110:buf_copy_input_to_output_rt.c= )
MOD_TMP112 = $(MOD_TMP111:buf_copy_scalar_to_mem_OL_1ch_rt.c= )
MOD_TMP113 = $(MOD_TMP112:buf_copy_scalar_to_mem_OL_rt.c= )
MOD_TMP114 = $(MOD_TMP113:buf_copy_scalar_to_mem_UL_1ch_rt.c= )
MOD_TMP115 = $(MOD_TMP114:buf_copy_scalar_to_mem_UL_rt.c= )
MOD_TMP116 = $(MOD_TMP115:buf_output_frame_1ch_rt.c= )
MOD_TMP117 = $(MOD_TMP116:buf_output_frame_rt.c= )
MOD_TMP118 = $(MOD_TMP117:buf_output_scalar_1ch_rt.c= )
MOD_TMP119 = $(MOD_TMP118:buf_output_scalar_rt.c= )
MOD_TMP120 = $(MOD_TMP119:svd_c_rt.c= )
MOD_TMP121 = $(MOD_TMP120:svd_d_rt.c= )
MOD_TMP122 = $(MOD_TMP121:svd_helper_rt.c= )
MOD_TMP123 = $(MOD_TMP122:svd_r_rt.c= )
MODULES_SRCS = $(MOD_TMP123:svd_z_rt.c= )
# Remove Opal-RT block sources from the list of S-Functions: they are provided with RT-LAB
# Leave any other S-Functions.
SFS_TMP1 = $(S_FUNCTIONS:recv_param.c=)
SFS_TMP1a = $(SFS_TMP1:RECV_Param.c=)
SFS_TMP2 = $(SFS_TMP1a:recv_rt.c=)
SFS_TMP3 = $(SFS_TMP2:op_send.c=)
SFS_TMP3a = $(SFS_TMP3:OP_SEND.c=)
SFS_TMP4 = $(SFS_TMP3a:send_rt.c=)
SFS_TMP10 = $(SFS_TMP4:sfun_timing.c=)
SFS_TMP11 = $(SFS_TMP10:optrigger.c=)
SFS_TMP19 = $(SFS_TMP11:opsnapshot.c=)
SFS_TMP20 = $(SFS_TMP19:opwritefile.c=)
SFS_TMP21 = $(SFS_TMP20:send_fw.c=)
SFS_TMP22 = $(SFS_TMP21:recv_fw.c=)
SFS_TMP23 = $(SFS_TMP22:simulation_info.c=)
SFS_TMP25 = $(SFS_TMP23:usr_delay.c=)
SFS_TMP26 = $(SFS_TMP25:simulation_events2.c=)
SFS_TMP56 = $(SFS_TMP26:sfun_opfromfile.c=)
SFS_TMP78 = $(SFS_TMP56:sfun_opexternvar.c=)
SFS_TMP79 = $(SFS_TMP78:sfun_time_factor.c=)
SFS_TMP80 = $(SFS_TMP79:sfun_ohci_info.c=)
SFS_TMP84 = $(SFS_TMP80:simulation_events.c=)
SFS_TMP88 = $(SFS_TMP84:sfun_sync_vme200_2.c=)
SFS_TMP92 = $(SFS_TMP88:read_dinamo.c=)
SFS_TMP93 = $(SFS_TMP92:sfun_subsystem_trigger.c=)
SFS_TMP110 = $(SFS_TMP93:sfun_async_st_emit.c=)
SFS_TMP127 = $(SFS_TMP110:recv_ohci.c=)
SFS_TMP128 = $(SFS_TMP127:send_ohci.c=)
SFS_TMP129 = $(SFS_TMP128:error_status.c=)
SFS_TMP130 = $(SFS_TMP129:fake_io.c=)
SFS_TMP131 = $(SFS_TMP130:op_getpid.c=)
SFS_TMP132 = $(SFS_TMP131:print_msg.c=)
SFS_TMP133 = $(SFS_TMP132:read_pport.c=)
SFS_TMP134 = $(SFS_TMP133:run_model.c=)
SFS_TMP138 = $(SFS_TMP134:opAssertion.c=)
SFS_TMP139 = $(SFS_TMP138:checkoutputwidth.c=)
SFS_TMP140 = $(SFS_TMP139:signalCompression.c=)
SFS_TMP141 = $(SFS_TMP140:signalUncompression.c=)
SFS_TMP142 = $(SFS_TMP141:opendianswapper.c=)
SFS_TMP143 = $(SFS_TMP142:signalcompression.c=)
SFS_TMP144 = $(SFS_TMP143:signaluncompression.c=)
SFS_TMP182 = $(SFS_TMP144:pause_model.c=)
SFS_TMP183 = $(SFS_TMP182:opmonitor.c=)
SFS_TMP215 = $(SFS_TMP183:mstack_ccp_cal.c=)
SFS_TMP216 = $(SFS_TMP215:mstack_ccp_in.c=)
SFS_TMP217 = $(SFS_TMP216:mstack_analog_in.c=)
SFS_TMP218 = $(SFS_TMP217:mstack_digital_in.c=)
SFS_TMP219 = $(SFS_TMP218:mstack_ccp_ctl.c=)
SFS_TMP229 = $(SFS_TMP219:pycall.c=)
SFS_TMP238 = $(SFS_TMP229:sfun_opdataset.c=)
SFS_TMP239 = $(SFS_TMP238:sfun_opinterpol.c=)
SFS_TMP240 = $(SFS_TMP239:nrt.c=)
SFS_TMP241 = $(SFS_TMP240:opplotfile.c=)
SFS_TMP242 = $(SFS_TMP241:pubhlaclassattr.c=)
SFS_TMP243 = $(SFS_TMP242:subhlaclassattr.c=)
SFS_TMP244 = $(SFS_TMP243:pubhlainteraction.c=)
SFS_TMP245 = $(SFS_TMP244:subhlainteraction.c=)
SFS_TMP246 = $(SFS_TMP245:pubentitytype.c=)
SFS_TMP247 = $(SFS_TMP246:hlafedoptions.c=)
SFS_TMP260 = $(SFS_TMP247:sfun_xplane.c=)
SFS_TMP261 = $(SFS_TMP260:sfun_opjoystick.c=)
SFS_TMP262 = $(SFS_TMP261:fts2abcd.c=)
SFS_TMP263 = $(SFS_TMP262:fts2flux.c=)
SFS_TMP264 = $(SFS_TMP263:fts2dla.c=)
SFS_TMP265 = $(SFS_TMP264:fts2hfun.c=)
SFS_TMP266 = $(SFS_TMP265:fts2abcd_dtc.c=)
SFS_TMP270 = $(SFS_TMP266:sfun_conversion.c=)
SFS_TMP271 = $(SFS_TMP270:sfun_elements_demux.c=)
SFS_TMP272 = $(SFS_TMP271:sfun_blob_decimation.c=)
SFS_TMP273 = $(SFS_TMP272:sfun_dynamic_rescale.c=)
SFS_TMP274 = $(SFS_TMP273:DBL2SFP.c=)
SFS_TMP275 = $(SFS_TMP274:SFP2DBL.c=)
SFS_TMP276 = $(SFS_TMP275:OpDVP.c=)
SFS_TMP277 = $(SFS_TMP276:OpRfm.c=)
SFS_TMP278 = $(SFS_TMP277:OpHei.c=)
SFS_TMP279 = $(SFS_TMP278:OpPickeringBattSim.c=)
S_FUNC_SRCS = $(SFS_TMP279:optaketime.c=)
#############################################################################
#
# For CarSim/VehSim/TruckSim by Mechanical SImulation Corp.
#
# The product name: MSC_PRODUCT_ID carsim, vehsim, trucksim
# The product type: MSC_PRODUCT_TYPE i_i, i_s__ss, s_ss ...
# Version Number: MSC_PRODUCT_VERSION 5.25, 6.02, 3.04 ...
#
#############################################################################
ifeq "$(MSC_PRODUCT_TYPE)" ""
# Do nothing here
else
include /usr/$(MSC_PRODUCT_ID)/$(MSC_PRODUCT_VERSION)/$(MSC_PRODUCT_ID).opt
endif
#
#############################################################################
# End CarSim/TruckSim/VehSim
#############################################################################
SHARED_SRC := $(subst \,/,$(SHARED_SRC))
SHARED_SRC := $(wildcard $(SHARED_SRC))
SHARED_SRC_DIR := $(subst \,/,$(SHARED_SRC_DIR))
ifeq ($(MODELREF_TARGET_TYPE), NONE)
# Top model for RTW
SRCS1 += $(MODEL).c model_main.c rt_sim.c $(RTWLOG) $(SOLVER) $(EXT_SRC) $(MODULES_SRCS) $(SHARED_SRC)
SRCS1 += $(INTERNAL_ADD_SOURCE_FILE) $(S_FUNC_SRCS) $(USER_SRCS)
SRCS = $(filter-out $(INTERNAL_IGN_SOURCE_FILE), $(SRCS1))
else
# sub-model for RTW
SRCS1 += $(MODULES_SRCS)
SRCS1 += $(INTERNAL_ADD_SOURCE_FILE) $(S_FUNC_SRCS) $(USER_SRCS)
SRCS = $(filter-out $(INTERNAL_IGN_SOURCE_FILE), $(SRCS1))
endif
ifeq "$(UNAME)" "QNX" ##### nto
ifeq ($(MODELREF_TARGET_TYPE), NONE)
include qnxnto.opt
else
include $(RELATIVE_PATH_TO_ANCHOR)/qnxnto.opt
endif
else
ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
MACHINE = $(shell uname -m)
ifeq "$(MACHINE)" "x86_64"
ifeq ($(MODELREF_TARGET_TYPE), NONE)
include linux64.opt
else
include $(RELATIVE_PATH_TO_ANCHOR)/linux64.opt
endif
else
ifeq ($(MODELREF_TARGET_TYPE), NONE)
include linux32.opt
else
include $(RELATIVE_PATH_TO_ANCHOR)/linux32.opt
endif
endif
else
ifeq ($(MODELREF_TARGET_TYPE), NONE)
include win32.opt
else
include $(RELATIVE_PATH_TO_ANCHOR)/OpNTtarget/win32.opt
endif
endif
endif
#------------------------------ Include Path -----------------------------
MATLAB_INCLUDES = -I$(TARGET_MATLAB_ROOT)/simulink/include \
-I$(TARGET_MATLAB_ROOT)/extern/include \
-I$(TARGET_MATLAB_ROOT)/rtw/c/src \
-I$(TARGET_MATLAB_ROOT)/rtw/c/src/matrixmath \
-I$(TARGET_MATLAB_ROOT)/rtw/c/libsrc \
ifeq "$(UNAME)" "QNX" ##### nto
MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/drive \
-I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/mech \
-I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/foundation \
-I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/network_engine \
-I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/ne_sli \
-I$(TARGET_MATLAB_ROOT)/toolbox/dspblks/include
else
ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/drive \
-I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/mech \
-I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/foundation \
-I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/network_engine \
-I$(TARGET_MATLAB_ROOT)/toolbox/simscape/include/ne_sli \
-I$(TARGET_MATLAB_ROOT)/toolbox/dspblks/include
else
MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/physmod/drive/c \
-I$(TARGET_MATLAB_ROOT)/toolbox/physmod/mech/c \
-I$(TARGET_MATLAB_ROOT)/toolbox/physmod/foundation/c \
-I$(TARGET_MATLAB_ROOT)/toolbox/physmod/ne_sli/c \
-I$(TARGET_MATLAB_ROOT)/toolbox/physmod/simscape/engine/sli/c \
-I$(TARGET_MATLAB_ROOT)/toolbox/physmod/network_engine/c
ifeq ($(OP_MATLABR2011A),1)
MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/dsp/include
else
ifeq ($(OP_MATLABR2011B),1)
MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/dsp/include
else
MATLAB_INCLUDES += -I$(TARGET_MATLAB_ROOT)/toolbox/dspblks/include
endif
endif
endif
endif
RTLAB_INCLUDES = \
-I$(TARGET_RTLAB_ROOT)/common/include \
-I$(TARGET_RTLAB_ROOT)/common/include_target \
-I$(TARGET_RTLAB_ROOT)/RT-LAB/include
SHARED_INCLUDES =
ifneq ($(SHARED_SRC_DIR),)
SHARED_INCLUDES = -I$(SHARED_SRC_DIR)
endif
INCLUDES = -I. $(MATLAB_INCLUDES) $(RTLAB_INCLUDES) $(INTERNAL_INCLUDE_PATH) $(USER_INCS) $(MODELREF_INC_PATH) $(SHARED_INCLUDES)
#------------------------ rtModel ----------------------------------------------
#define USE_RTMODEL 1
RTM_CC_OPTS = -DUSE_RTMODEL
ifeq ($(OP_DISCRETE_SOLVER),1)
RTM_CC_OPTS = -DUSE_RTMODEL -DDISCRETE_SOLVER
endif
#-------------------------------- C Flags --------------------------------
# General User Options
#OLDMATLABVERSION = 0
ifeq ($(OP_MATLABR2006B),1)
MATLABVERSION_CFLAGS = -DOP_MATLABR2006B
#OLDMATLABVERSION = 1
endif
ifeq ($(OP_MATLABR2007B),1)
MATLABVERSION_CFLAGS = -DOP_MATLABR2007B
#OLDMATLABVERSION = 1
endif
ifeq ($(OP_MATLABR2008A),1)
MATLABVERSION_CFLAGS = -DOP_MATLABR2008A
endif
ifeq ($(OP_MATLABR2008B),1)
MATLABVERSION_CFLAGS = -DOP_MATLABR2008B
endif
ifeq ($(OP_MATLABR2009B),1)
MATLABVERSION_CFLAGS = -DOP_MATLABR2009B
endif
ifeq ($(OP_MATLABR2010A),1)
MATLABVERSION_CFLAGS = -DOP_MATLABR2010A
endif
ifeq ($(OP_MATLABR2010B),1)
MATLABVERSION_CFLAGS = -DOP_MATLABR2010B
endif
ifeq ($(OP_MATLABR2011A),1)
MATLABVERSION_CFLAGS = -DOP_MATLABR2011A
endif
ifeq ($(OP_MATLABR2011B),1)
MATLABVERSION_CFLAGS = -DOP_MATLABR2011B
endif
OPTS =
ANSI_OPTS =
CC_OPTS = -c $(OPT_OPTS) $(OPTS) $(ANSI_OPTS) $(EXT_CC_OPTS) $(RTM_CC_OPTS)
CC_OPTS77 = -c $(OPT_OPTS77) $(OPTS) $(ANSI_OPTS) $(EXT_CC_OPTS) $(RTM_CC_OPTS)
CPP_REQ_DEFINES = -DMODEL=$(MODEL) -DRT=RT -DNUMST=$(NUMST) \
-DTID01EQ=$(TID01EQ) -DNCSTATES=$(NCSTATES) \
-DMULTITASKING=$(MULTITASKING) -D_SIMULINK -DRTLAB $(MATLABVERSION_CFLAGS)
CFLAGS = $(CC_OPTS) $(CPP_REQ_DEFINES) $(TARGET_CFLAGS) $(INCLUDES)
CFLAGS77 = $(CC_OPTS77) $(CPP_REQ_DEFINES) $(TARGET_CFLAGS) $(INCLUDES)
#------------------------------- LD Flags --------------------------------
LDFLAGS = $(LD_DEBUG_OPTS) $(LIBPATH) $(EXT_LD_OPTS) $(RTLAB_LDFLAGS)
#--------------------------------- Rules ---------------------------------
ifeq "$(UNAME)" "QNX" ##### nto
ifeq ($(MODELREF_TARGET_TYPE), NONE)
include posix.rules
else
include $(RELATIVE_PATH_TO_ANCHOR)/posix.rules
endif
else
ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
ifeq ($(MODELREF_TARGET_TYPE), NONE)
include posix.rules
else
include $(RELATIVE_PATH_TO_ANCHOR)/posix.rules
endif
else
ifeq ($(MODELREF_TARGET_TYPE), NONE)
include win32.rules
else
include $(RELATIVE_PATH_TO_ANCHOR)/OpNTtarget/win32.rules
endif
# Libraries:
ifeq ($(USE_EXPAND_RTWLIB),1)
else
MODULES_rtwlib = rt_backsubcc_dbl.obj \
rt_backsubcc_sgl.obj \
rt_backsubrc_dbl.obj \
rt_backsubrc_sgl.obj \
rt_backsubrr_dbl.obj \
rt_backsubrr_sgl.obj \
rt_forwardsubcc_dbl.obj \
rt_forwardsubcc_sgl.obj \
rt_forwardsubcr_dbl.obj \
rt_forwardsubcr_sgl.obj \
rt_forwardsubrc_dbl.obj \
rt_forwardsubrc_sgl.obj \
rt_forwardsubrr_dbl.obj \
rt_forwardsubrr_sgl.obj \
rt_lu_cplx.obj \
rt_lu_cplx_sgl.obj \
rt_lu_real.obj \
rt_lu_real_sgl.obj \
rt_matdivcc_dbl.obj \
rt_matdivcc_sgl.obj \
rt_matdivcr_dbl.obj \
rt_matdivcr_sgl.obj \
rt_matdivrc_dbl.obj \
rt_matdivrc_sgl.obj \
rt_matdivrr_dbl.obj \
rt_matdivrr_sgl.obj \
rt_matmultandinccc_dbl.obj \
rt_matmultandinccc_sgl.obj \
rt_matmultandinccr_dbl.obj \
rt_matmultandinccr_sgl.obj \
rt_matmultandincrc_dbl.obj \
rt_matmultandincrc_sgl.obj \
rt_matmultandincrr_dbl.obj \
rt_matmultandincrr_sgl.obj \
rt_matmultcc_dbl.obj \
rt_matmultcc_sgl.obj \
rt_matmultcr_dbl.obj \
rt_matmultcr_sgl.obj \
rt_matmultrc_dbl.obj \
rt_matmultrc_sgl.obj \
rt_matmultrr_dbl.obj \
rt_matmultrr_sgl.obj
endif
$(RTWLIB) :
@echo ### Creating $@
ifeq ($(USE_EXPAND_RTWLIB),1)
$(CC) $(CFLAGS) $(ALT_MATLAB_ROOT)\rtw\c\libsrc\*.c
else
$(CC) $(CFLAGS) $(ALT_MATLAB_ROOT)\rtw\c\src\matrixmath\*.c
endif
$(LIBCMD) /nologo /out:$@ $(MODULES_rtwlib)
@echo ### Created $@
endif
endif
ifeq "$(UNAME)" "QNX" ##### nto
MODELREF_LINK_LIBS_MAIN :
@for A in $(MODELREFS); do $(MAKE) -C $(SHARED_SRC_DIR)/../$$A -f $$A.mk; done
else
ifeq "$(UNAME)" "Linux" ##### Linux (RedHawk)
MODELREF_LINK_LIBS_MAIN :
@for A in $(MODELREFS); do $(MAKE) -C $(SHARED_SRC_DIR)/../$$A -f $$A.mk; done
else
MODELREF_LINK_LIBS_MAIN :
@FOR %A IN ($(MODELREFS)) DO $(MAKE) -C $(SHARED_SRC_DIR)/../%A -f %A.mk
endif
endif

1
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test.nvcmd
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@ -1 +0,0 @@
!/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/asyncip_sl_1_sm_ip_test 5e-005 1 6946817 327785 1 2 137.226.160.105:57515 8404994

46
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123701.log
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@ -1,46 +0,0 @@
**************************************************************************
** Execution log file generated by RT-LAB on Wed May 28 12:37:01 2014
**************************************************************************
Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
12 CPUs active on this Computer
libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
Highest active CPU: 12
Subsystem sm_ip_test allocates 1 cores.
model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
Monitoring is enabled
RECV: connection to host established
SEND: connection to host established
Display of standard output will be disabled
AsyncIP: Version : Opal-RT_20060524
AsyncIP: Protocol : UDP/IP
AsyncIP: Remote Address : 137.226.160.91
AsyncIP: Remote Port : 10200
AsyncIP: Local Port : 10201
AsyncIP: SendToIPPort thread started
AsyncIP: RecvFromIPPort thread started
SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
Synchronized with software timer.
Real-time SingleTasking mode.
RT-LAB license ok. Unlimited time license.
Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
[0]: PAUSE mode, IO set to pause value.
Total of 0 Overrun detected.
Wed May 28 12:37:02 2014
[1]: RUN mode, IO set to run value.
Synchronized step size = 50 us.
Wed May 28 12:37:08 2014
Main priority set to 99
[1919869]: PAUSE mode, IO set to pause value.
Total of 0 Overrun detected.
Wed May 28 12:38:44 2014
[1919869]: Reset
Total of 0 Overrun detected.
Wed May 28 12:39:03 2014
AsyncIP: SendToIPPort: Finished
AsyncIP: RecvFromIPPort: Finished
Reset done

42
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_123901.log
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@ -1,42 +0,0 @@
**************************************************************************
** Execution log file generated by RT-LAB on Wed May 28 12:39:01 2014
**************************************************************************
Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
12 CPUs active on this Computer
libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
Highest active CPU: 12
Subsystem sm_ip_test allocates 1 cores.
model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
Monitoring is enabled
RECV: connection to host established
SEND: connection to host established
Display of standard output will be disabled
AsyncIP: Version : Opal-RT_20060524
AsyncIP: Protocol : UDP/IP
AsyncIP: Remote Address : 137.226.160.91
AsyncIP: Remote Port : 10200
AsyncIP: Local Port : 10201
AsyncIP: SendToIPPort thread started
AsyncIP: RecvFromIPPort thread started
SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
Synchronized with software timer.
Real-time SingleTasking mode.
RT-LAB license ok. Unlimited time license.
Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
[0]: PAUSE mode, IO set to pause value.
Total of 0 Overrun detected.
Wed May 28 12:39:01 2014
[1]: RUN mode, IO set to run value.
Synchronized step size = 50 us.
Wed May 28 12:39:30 2014
Main priority set to 99
[2861676]: Reset
Total of 0 Overrun detected.
Wed May 28 12:41:53 2014
AsyncIP: SendToIPPort: Finished
AsyncIP: RecvFromIPPort: Finished
Reset done

46
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_124401.log
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@ -1,46 +0,0 @@
**************************************************************************
** Execution log file generated by RT-LAB on Wed May 28 12:44:01 2014
**************************************************************************
Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
12 CPUs active on this Computer
libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
Highest active CPU: 12
Subsystem sm_ip_test allocates 1 cores.
model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
Monitoring is enabled
RECV: connection to host established
SEND: connection to host established
Display of standard output will be disabled
AsyncIP: Version : Opal-RT_20060524
AsyncIP: Protocol : UDP/IP
AsyncIP: Remote Address : 137.226.160.91
AsyncIP: Remote Port : 10200
AsyncIP: Local Port : 10201
AsyncIP: SendToIPPort thread started
AsyncIP: RecvFromIPPort thread started
SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
Synchronized with software timer.
Real-time SingleTasking mode.
RT-LAB license ok. Unlimited time license.
Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
[0]: PAUSE mode, IO set to pause value.
Total of 0 Overrun detected.
Wed May 28 12:44:01 2014
[1]: RUN mode, IO set to run value.
Synchronized step size = 50 us.
Wed May 28 12:44:06 2014
Main priority set to 99
[6943768]: PAUSE mode, IO set to pause value.
Total of 0 Overrun detected.
Wed May 28 12:49:54 2014
[6943768]: Reset
Total of 0 Overrun detected.
Wed May 28 12:49:56 2014
AsyncIP: SendToIPPort: Finished
AsyncIP: RecvFromIPPort: Finished
Reset done

42
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125001.log
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@ -1,42 +0,0 @@
**************************************************************************
** Execution log file generated by RT-LAB on Wed May 28 12:50:01 2014
**************************************************************************
Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
12 CPUs active on this Computer
libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
Highest active CPU: 12
Subsystem sm_ip_test allocates 1 cores.
model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
Monitoring is enabled
RECV: connection to host established
SEND: connection to host established
Display of standard output will be disabled
AsyncIP: Version : Opal-RT_20060524
AsyncIP: Protocol : UDP/IP
AsyncIP: Remote Address : 137.226.160.91
AsyncIP: Remote Port : 10200
AsyncIP: Local Port : 10201
AsyncIP: SendToIPPort thread started
AsyncIP: RecvFromIPPort thread started
SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
Synchronized with software timer.
Real-time SingleTasking mode.
RT-LAB license ok. Unlimited time license.
Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
[0]: PAUSE mode, IO set to pause value.
Total of 0 Overrun detected.
Wed May 28 12:50:01 2014
[1]: RUN mode, IO set to run value.
Synchronized step size = 50 us.
Wed May 28 12:50:04 2014
Main priority set to 99
[2816109]: Reset
Total of 0 Overrun detected.
Wed May 28 12:52:24 2014
AsyncIP: SendToIPPort: Finished
AsyncIP: RecvFromIPPort: Finished
Reset done

42
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_147_125401.log
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@ -1,42 +0,0 @@
**************************************************************************
** Execution log file generated by RT-LAB on Wed May 28 12:54:01 2014
**************************************************************************
Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
12 CPUs active on this Computer
libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
Highest active CPU: 12
Subsystem sm_ip_test allocates 1 cores.
model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
Monitoring is enabled
RECV: connection to host established
SEND: connection to host established
Display of standard output will be disabled
AsyncIP: Version : Opal-RT_20060524
AsyncIP: Protocol : UDP/IP
AsyncIP: Remote Address : 137.226.160.91
AsyncIP: Remote Port : 10200
AsyncIP: Local Port : 10201
AsyncIP: SendToIPPort thread started
AsyncIP: RecvFromIPPort thread started
SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
Synchronized with software timer.
Real-time SingleTasking mode.
RT-LAB license ok. Unlimited time license.
Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
[0]: PAUSE mode, IO set to pause value.
Total of 0 Overrun detected.
Wed May 28 12:54:01 2014
[1]: RUN mode, IO set to run value.
Synchronized step size = 50 us.
Wed May 28 12:54:24 2014
Main priority set to 99
AsyncIP: SendToIPPort: Finished
[17891814]: Reset
Total of 0 Overrun detected.
Wed May 28 13:09:18 2014
AsyncIP: RecvFromIPPort: Finished
Reset done

480
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_data.c
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@ -1,480 +0,0 @@
/*
* asyncip_sl_1_sm_ip_test_data.c
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#include "asyncip_sl_1_sm_ip_test.h"
#include "asyncip_sl_1_sm_ip_test_private.h"
/* Block parameters (auto storage) */
Parameters_asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test_P = {
0.0, /* Expression: 0
* Referenced by: '<S1>/S-Function1'
*/
0.0, /* Expression: 0
* Referenced by: '<S1>/S-Function'
*/
1.0, /* Expression: 1
* Referenced by: '<S2>/data ready 1 kHz'
*/
2.0, /* Expression: 2
* Referenced by: '<S2>/data ready 1 kHz'
*/
1.0, /* Expression: 1
* Referenced by: '<S2>/data ready 1 kHz'
*/
0.0, /* Expression: 0
* Referenced by: '<S2>/data ready 1 kHz'
*/
/* Expression: [1 2 3 4]
* Referenced by: '<S2>/constants'
*/
{ 1.0, 2.0, 3.0, 4.0 },
5.0, /* Expression: 5
* Referenced by: '<S2>/Pulse Generator'
*/
2000.0, /* Computed Parameter: PulseGenerator_Period
* Referenced by: '<S2>/Pulse Generator'
*/
600.0, /* Computed Parameter: PulseGenerator_Duty
* Referenced by: '<S2>/Pulse Generator'
*/
0.0, /* Expression: 0
* Referenced by: '<S2>/Pulse Generator'
*/
/* Computed Parameter: SFunction2_P1_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 1.0 },
1.0, /* Expression: ctl_id
* Referenced by: '<S5>/S-Function2'
*/
/* Computed Parameter: SFunction2_P2_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 1.0 },
1.0, /* Expression: send_id
* Referenced by: '<S5>/S-Function2'
*/
/* Computed Parameter: SFunction2_P3_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 1.0 },
3.0, /* Expression: mode
* Referenced by: '<S5>/S-Function2'
*/
/* Computed Parameter: SFunction2_P4_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 1.0 },
1.0, /* Expression: fp1
* Referenced by: '<S5>/S-Function2'
*/
/* Computed Parameter: SFunction2_P5_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 1.0 },
2.0, /* Expression: fp2
* Referenced by: '<S5>/S-Function2'
*/
/* Computed Parameter: SFunction2_P6_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 1.0 },
3.0, /* Expression: fp3
* Referenced by: '<S5>/S-Function2'
*/
/* Computed Parameter: SFunction2_P7_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 1.0 },
4.0, /* Expression: fp4
* Referenced by: '<S5>/S-Function2'
*/
/* Computed Parameter: SFunction2_P8_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 1.0 },
5.0, /* Expression: fp5
* Referenced by: '<S5>/S-Function2'
*/
/* Computed Parameter: SFunction2_P9_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction2_P9
* Referenced by: '<S5>/S-Function2'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 49.0 },
/* Computed Parameter: SFunction2_P10_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction2_P10
* Referenced by: '<S5>/S-Function2'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 50.0 },
/* Computed Parameter: SFunction2_P11_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction2_P11
* Referenced by: '<S5>/S-Function2'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 51.0 },
/* Computed Parameter: SFunction2_P12_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction2_P12
* Referenced by: '<S5>/S-Function2'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 52.0 },
/* Computed Parameter: SFunction2_P13_Size
* Referenced by: '<S5>/S-Function2'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction2_P13
* Referenced by: '<S5>/S-Function2'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 53.0 },
2.0, /* Expression: 2
* Referenced by: '<S2>/timeout'
*/
/* Computed Parameter: SFunction1_P1_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 1.0 },
1.0, /* Expression: ctl_id
* Referenced by: '<S3>/S-Function1'
*/
/* Computed Parameter: SFunction1_P2_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 1.0 },
1.0, /* Expression: recv_id
* Referenced by: '<S3>/S-Function1'
*/
/* Computed Parameter: SFunction1_P3_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 1.0 },
1.0, /* Expression: fp1
* Referenced by: '<S3>/S-Function1'
*/
/* Computed Parameter: SFunction1_P4_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 1.0 },
2.0, /* Expression: fp2
* Referenced by: '<S3>/S-Function1'
*/
/* Computed Parameter: SFunction1_P5_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 1.0 },
3.0, /* Expression: fp3
* Referenced by: '<S3>/S-Function1'
*/
/* Computed Parameter: SFunction1_P6_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 1.0 },
4.0, /* Expression: fp4
* Referenced by: '<S3>/S-Function1'
*/
/* Computed Parameter: SFunction1_P7_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 1.0 },
5.0, /* Expression: fp5
* Referenced by: '<S3>/S-Function1'
*/
/* Computed Parameter: SFunction1_P8_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction1_P8
* Referenced by: '<S3>/S-Function1'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 49.0 },
/* Computed Parameter: SFunction1_P9_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction1_P9
* Referenced by: '<S3>/S-Function1'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 50.0 },
/* Computed Parameter: SFunction1_P10_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction1_P10
* Referenced by: '<S3>/S-Function1'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 51.0 },
/* Computed Parameter: SFunction1_P11_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction1_P11
* Referenced by: '<S3>/S-Function1'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 52.0 },
/* Computed Parameter: SFunction1_P12_Size
* Referenced by: '<S3>/S-Function1'
*/
{ 1.0, 7.0 },
/* Computed Parameter: SFunction1_P12
* Referenced by: '<S3>/S-Function1'
*/
{ 115.0, 116.0, 114.0, 105.0, 110.0, 103.0, 53.0 },
/* Computed Parameter: SFunction_P1_Size
* Referenced by: '<S7>/S-Function'
*/
{ 1.0, 1.0 },
1.0, /* Expression: Acqu_group
* Referenced by: '<S7>/S-Function'
*/
/* Computed Parameter: OpIPSocketCtrl1_P1_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
1.0, /* Expression: ctl_id
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P2_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
1.0, /* Expression: proto
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P3_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
10200.0, /* Expression: ip_port_remote
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P4_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
10201.0, /* Expression: ip_port_local
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P5_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0, /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P6_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0, /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P7_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0, /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P8_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0, /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P9_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0, /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P10_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0, /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P11_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0, /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P12_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0, /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P13_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0, /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
/* Computed Parameter: OpIPSocketCtrl1_P14_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 14.0 },
/* Computed Parameter: OpIPSocketCtrl1_P14
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 49.0, 51.0, 55.0, 46.0, 50.0, 50.0, 54.0, 46.0, 49.0, 54.0, 48.0, 46.0, 57.0,
49.0 },
/* Computed Parameter: OpIPSocketCtrl1_P15_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 7.0 },
/* Computed Parameter: OpIPSocketCtrl1_P15
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 48.0, 46.0, 48.0, 46.0, 48.0, 46.0, 48.0 },
/* Computed Parameter: OpIPSocketCtrl1_P16_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P17_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P18_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P19_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P20_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P21_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P22_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P23_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P24_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P25_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 0.0, 0.0 },
/* Computed Parameter: OpIPSocketCtrl1_P26_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 7.0 },
/* Computed Parameter: OpIPSocketCtrl1_P26
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 65.0, 115.0, 121.0, 110.0, 99.0, 73.0, 80.0 },
/* Computed Parameter: OpIPSocketCtrl1_P27_Size
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
{ 1.0, 1.0 },
0.0 /* Expression: 0
* Referenced by: '<S2>/OpIPSocketCtrl1'
*/
};

42
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_last_simulation.log
View file

@ -1,42 +0,0 @@
**************************************************************************
** Execution log file generated by RT-LAB on Wed May 28 12:54:01 2014
**************************************************************************
Model 'asyncip_sl_1_sm_ip_test' compiled in RELEASE mode.
12 CPUs active on this Computer
libOpalR2011B.a : v10.5.9.356 (build = 20130508211918)
Highest active CPU: 12
Subsystem sm_ip_test allocates 1 cores.
model asyncip_sl_1_sm_ip_test assigned to logical cpu 1
Monitoring is enabled
RECV: connection to host established
SEND: connection to host established
Display of standard output will be disabled
AsyncIP: Version : Opal-RT_20060524
AsyncIP: Protocol : UDP/IP
AsyncIP: Remote Address : 137.226.160.91
AsyncIP: Remote Port : 10200
AsyncIP: Local Port : 10201
AsyncIP: SendToIPPort thread started
AsyncIP: RecvFromIPPort thread started
SubSystem step size = 0.000050 sec. Status updated at every 1 local step.
Synchronized with software timer.
Real-time SingleTasking mode.
RT-LAB license ok. Unlimited time license.
Snapshot taken (opasyncip_sl_sm_ip_test_0.snap).
[0]: PAUSE mode, IO set to pause value.
Total of 0 Overrun detected.
Wed May 28 12:54:01 2014
[1]: RUN mode, IO set to run value.
Synchronized step size = 50 us.
Wed May 28 12:54:24 2014
Main priority set to 99
AsyncIP: SendToIPPort: Finished
[17891814]: Reset
Total of 0 Overrun detected.
Wed May 28 13:09:18 2014
AsyncIP: RecvFromIPPort: Finished
Reset done

38
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_private.h
View file

@ -1,38 +0,0 @@
/*
* asyncip_sl_1_sm_ip_test_private.h
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#ifndef RTW_HEADER_asyncip_sl_1_sm_ip_test_private_h_
#define RTW_HEADER_asyncip_sl_1_sm_ip_test_private_h_
#include "rtwtypes.h"
#ifndef __RTWTYPES_H__
#error This file requires rtwtypes.h to be included
#else
#ifdef TMWTYPES_PREVIOUSLY_INCLUDED
#error This file requires rtwtypes.h to be included before tmwtypes.h
#else
/* Check for inclusion of an incorrect version of rtwtypes.h */
#ifndef RTWTYPES_ID_C08S16I32L32N32F1
#error This code was generated with a different "rtwtypes.h" than the file included
#endif /* RTWTYPES_ID_C08S16I32L32N32F1 */
#endif /* TMWTYPES_PREVIOUSLY_INCLUDED */
#endif /* __RTWTYPES_H__ */
extern void sfun_send_async(SimStruct *rts);
extern void sfun_recv_async(SimStruct *rts);
extern void OP_SEND(SimStruct *rts);
extern void sfun_gen_async_ctrl(SimStruct *rts);
#endif /* RTW_HEADER_asyncip_sl_1_sm_ip_test_private_h_ */

0
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_ref.rsp
View file

27
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/asyncip_sl_1_sm_ip_test_types.h
View file

@ -1,27 +0,0 @@
/*
* asyncip_sl_1_sm_ip_test_types.h
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#ifndef RTW_HEADER_asyncip_sl_1_sm_ip_test_types_h_
#define RTW_HEADER_asyncip_sl_1_sm_ip_test_types_h_
#include "rtwtypes.h"
/* Parameters (auto storage) */
typedef struct Parameters_asyncip_sl_1_sm_ip_test_
Parameters_asyncip_sl_1_sm_ip_test;
/* Forward declaration for rtModel */
typedef struct RT_MODEL_asyncip_sl_1_sm_ip_test RT_MODEL_asyncip_sl_1_sm_ip_test;
#endif /* RTW_HEADER_asyncip_sl_1_sm_ip_test_types_h_ */

BIN
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/buildInfo.mat
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648
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/compilation_target_report.xml
View file

@ -1,648 +0,0 @@
<?xml version="1.0" encoding="utf-8"?>
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<property name="Model name">
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</property>
<property name="Model name">
<value>
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</value>
</property>
<property name="Physical ID">
<value>
1
</value>
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<property name="Processor ID">
<value>
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</value>
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<property name="Speed">
<value>
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</value>
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<property name="Vendor ID">
<value>
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</value>
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</item>
</item>
</item>
<item name="Network and internet">
<item name="Network">
<item name="General information">
<property name="Computer name">
<value>
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</value>
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<property name="Local IP">
<value>
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</value>
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</item>
</item>
</item>
<item name="Software system">
<item name="Installed programs">
<item name="ARTEMIS"/>
<item name="Gcc">
<property name="Current version">
<value>
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</item>
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<property name="Current version">
<value>
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</item>
<item name="Operating system">
<property name="Release">
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<property name="Type">
<value>
linux2
</value>
</property>
<property name="Version">
<value>
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</item>
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</item>
</item>
</item>
</item>
</item>
</item>

8
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/defines.txt
View file

@ -1,8 +0,0 @@
MODEL=asyncip_sl_1_sm_ip_test
NUMST=2
NCSTATES=0
HAVESTDIO
RT
USE_RTMODEL
INTEGER_CODE=0
MT=0

1
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/modelsources.txt
View file

@ -1 +0,0 @@
asyncip_sl_1_sm_ip_test.c rt_matrx.c rt_printf.c rt_logging.c

BIN
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/opasyncip_sl_sm_ip_test_0.snap
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140
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.c
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@ -1,140 +0,0 @@
/*
* rtGetInf.c
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
/*
* Abstract:
* Function to intialize non-finite, Inf
*/
#include "rtGetInf.h"
#define NumBitsPerChar 8U
/*
* Initialize rtInf needed by the generated code.
* Inf is initialized as non-signaling. Assumes IEEE.
*/
real_T rtGetInf(void)
{
size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
real_T inf = 0.0;
if (bitsPerReal == 32U) {
inf = rtGetInfF();
} else {
uint16_T one = 1U;
enum {
LittleEndian,
BigEndian
} machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;
switch (machByteOrder) {
case LittleEndian:
{
union {
LittleEndianIEEEDouble bitVal;
real_T fltVal;
} tmpVal;
tmpVal.bitVal.words.wordH = 0x7FF00000U;
tmpVal.bitVal.words.wordL = 0x00000000U;
inf = tmpVal.fltVal;
break;
}
case BigEndian:
{
union {
BigEndianIEEEDouble bitVal;
real_T fltVal;
} tmpVal;
tmpVal.bitVal.words.wordH = 0x7FF00000U;
tmpVal.bitVal.words.wordL = 0x00000000U;
inf = tmpVal.fltVal;
break;
}
}
}
return inf;
}
/*
* Initialize rtInfF needed by the generated code.
* Inf is initialized as non-signaling. Assumes IEEE.
*/
real32_T rtGetInfF(void)
{
IEEESingle infF;
infF.wordL.wordLuint = 0x7F800000U;
return infF.wordL.wordLreal;
}
/*
* Initialize rtMinusInf needed by the generated code.
* Inf is initialized as non-signaling. Assumes IEEE.
*/
real_T rtGetMinusInf(void)
{
size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
real_T minf = 0.0;
if (bitsPerReal == 32U) {
minf = rtGetMinusInfF();
} else {
uint16_T one = 1U;
enum {
LittleEndian,
BigEndian
} machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;
switch (machByteOrder) {
case LittleEndian:
{
union {
LittleEndianIEEEDouble bitVal;
real_T fltVal;
} tmpVal;
tmpVal.bitVal.words.wordH = 0xFFF00000U;
tmpVal.bitVal.words.wordL = 0x00000000U;
minf = tmpVal.fltVal;
break;
}
case BigEndian:
{
union {
BigEndianIEEEDouble bitVal;
real_T fltVal;
} tmpVal;
tmpVal.bitVal.words.wordH = 0xFFF00000U;
tmpVal.bitVal.words.wordL = 0x00000000U;
minf = tmpVal.fltVal;
break;
}
}
}
return minf;
}
/*
* Initialize rtMinusInfF needed by the generated code.
* Inf is initialized as non-signaling. Assumes IEEE.
*/
real32_T rtGetMinusInfF(void)
{
IEEESingle minfF;
minfF.wordL.wordLuint = 0xFF800000U;
return minfF.wordL.wordLreal;
}

28
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetInf.h
View file

@ -1,28 +0,0 @@
/*
* rtGetInf.h
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#ifndef RTW_HEADER_rtGetInf_h_
#define RTW_HEADER_rtGetInf_h_
#include <stddef.h>
#include "rtwtypes.h"
#include "rt_nonfinite.h"
extern real_T rtGetInf(void);
extern real32_T rtGetInfF(void);
extern real_T rtGetMinusInf(void);
extern real32_T rtGetMinusInfF(void);
#endif /* RTW_HEADER_rtGetInf_h_ */

100
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.c
View file

@ -1,100 +0,0 @@
/*
* rtGetNaN.c
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
/*
* Abstract:
* Function to intialize non-finite, NaN
*/
#include "rtGetNaN.h"
#define NumBitsPerChar 8U
/*
* Initialize rtNaN needed by the generated code.
* NaN is initialized as non-signaling. Assumes IEEE.
*/
real_T rtGetNaN(void)
{
size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
real_T nan = 0.0;
if (bitsPerReal == 32U) {
nan = rtGetNaNF();
} else {
uint16_T one = 1U;
enum {
LittleEndian,
BigEndian
} machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;
switch (machByteOrder) {
case LittleEndian:
{
union {
LittleEndianIEEEDouble bitVal;
real_T fltVal;
} tmpVal;
tmpVal.bitVal.words.wordH = 0xFFF80000U;
tmpVal.bitVal.words.wordL = 0x00000000U;
nan = tmpVal.fltVal;
break;
}
case BigEndian:
{
union {
BigEndianIEEEDouble bitVal;
real_T fltVal;
} tmpVal;
tmpVal.bitVal.words.wordH = 0x7FFFFFFFU;
tmpVal.bitVal.words.wordL = 0xFFFFFFFFU;
nan = tmpVal.fltVal;
break;
}
}
}
return nan;
}
/*
* Initialize rtNaNF needed by the generated code.
* NaN is initialized as non-signaling. Assumes IEEE.
*/
real32_T rtGetNaNF(void)
{
IEEESingle nanF = { { 0 } };
uint16_T one = 1U;
enum {
LittleEndian,
BigEndian
} machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian;
switch (machByteOrder) {
case LittleEndian:
{
nanF.wordL.wordLuint = 0xFFC00000U;
break;
}
case BigEndian:
{
nanF.wordL.wordLuint = 0x7FFFFFFFU;
break;
}
}
return nanF.wordL.wordLreal;
}

26
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtGetNaN.h
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@ -1,26 +0,0 @@
/*
* rtGetNaN.h
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#ifndef RTW_HEADER_rtGetNaN_h_
#define RTW_HEADER_rtGetNaN_h_
#include <stddef.h>
#include "rtwtypes.h"
#include "rt_nonfinite.h"
extern real_T rtGetNaN(void);
extern real32_T rtGetNaNF(void);
#endif /* RTW_HEADER_rtGetNaN_h_ */

49
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_defines.h
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@ -1,49 +0,0 @@
/*
* rt_defines.h
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#ifndef RTW_HEADER_rt_defines_h_
#define RTW_HEADER_rt_defines_h_
/*===========*
* Constants *
*===========*/
#define RT_PI 3.14159265358979323846
#define RT_PIF 3.1415927F
#define RT_LN_10 2.30258509299404568402
#define RT_LN_10F 2.3025851F
#define RT_LOG10E 0.43429448190325182765
#define RT_LOG10EF 0.43429449F
#define RT_E 2.7182818284590452354
#define RT_EF 2.7182817F
/*
* UNUSED_PARAMETER(x)
* Used to specify that a function parameter (argument) is required but not
* accessed by the function body.
*/
#ifndef UNUSED_PARAMETER
# if defined(__LCC__)
# define UNUSED_PARAMETER(x) /* do nothing */
# else
/*
* This is the semi-ANSI standard way of indicating that an
* unused function parameter is required.
*/
# define UNUSED_PARAMETER(x) (void) (x)
# endif
#endif
#endif /* RTW_HEADER_rt_defines_h_ */

70
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.c
View file

@ -1,70 +0,0 @@
/*
* rt_nonfinite.c
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
/*
* Abstract:
* Function to intialize non-finites,
* (Inf, NaN and -Inf).
*/
#include "rt_nonfinite.h"
#include "rtGetNaN.h"
#include "rtGetInf.h"
real_T rtInf;
real_T rtMinusInf;
real_T rtNaN;
real32_T rtInfF;
real32_T rtMinusInfF;
real32_T rtNaNF;
/*
* Initialize the rtInf, rtMinusInf, and rtNaN needed by the
* generated code. NaN is initialized as non-signaling. Assumes IEEE.
*/
void rt_InitInfAndNaN(size_t realSize)
{
(void) (realSize);
rtNaN = rtGetNaN();
rtNaNF = rtGetNaNF();
rtInf = rtGetInf();
rtInfF = rtGetInfF();
rtMinusInf = rtGetMinusInf();
rtMinusInfF = rtGetMinusInfF();
}
/* Test if value is infinite */
boolean_T rtIsInf(real_T value)
{
return (boolean_T)((value==rtInf || value==rtMinusInf) ? 1U : 0U);
}
/* Test if single-precision value is infinite */
boolean_T rtIsInfF(real32_T value)
{
return (boolean_T)(((value)==rtInfF || (value)==rtMinusInfF) ? 1U : 0U);
}
/* Test if value is not a number */
boolean_T rtIsNaN(real_T value)
{
return (boolean_T)((value!=value) ? 1U : 0U);
}
/* Test if single-precision value is not a number */
boolean_T rtIsNaNF(real32_T value)
{
return (boolean_T)(((value!=value) ? 1U : 0U));
}

54
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rt_nonfinite.h
View file

@ -1,54 +0,0 @@
/*
* rt_nonfinite.h
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#ifndef RTW_HEADER_rt_nonfinite_h_
#define RTW_HEADER_rt_nonfinite_h_
#include <stddef.h>
#include "rtwtypes.h"
extern real_T rtInf;
extern real_T rtMinusInf;
extern real_T rtNaN;
extern real32_T rtInfF;
extern real32_T rtMinusInfF;
extern real32_T rtNaNF;
extern void rt_InitInfAndNaN(size_t realSize);
extern boolean_T rtIsInf(real_T value);
extern boolean_T rtIsInfF(real32_T value);
extern boolean_T rtIsNaN(real_T value);
extern boolean_T rtIsNaNF(real32_T value);
typedef struct {
struct {
uint32_T wordH;
uint32_T wordL;
} words;
} BigEndianIEEEDouble;
typedef struct {
struct {
uint32_T wordL;
uint32_T wordH;
} words;
} LittleEndianIEEEDouble;
typedef struct {
union {
real32_T wordLreal;
uint32_T wordLuint;
} wordL;
} IEEESingle;
#endif /* RTW_HEADER_rt_nonfinite_h_ */

23
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtmodel.h
View file

@ -1,23 +0,0 @@
/*
* rtmodel.h:
*
* Code generation for model "asyncip_sl_1_sm_ip_test.mdl".
*
* Model version : 1.426
* Simulink Coder version : 8.1 (R2011b) 08-Jul-2011
* C source code generated on : Wed May 28 12:53:42 2014
*
* Target selection: rtlab_rtmodel.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#ifndef RTW_HEADER_rtmodel_h_
#define RTW_HEADER_rtmodel_h_
/*
* Includes the appropriate headers when we are using rtModel
*/
#include "asyncip_sl_1_sm_ip_test.h"
#endif /* RTW_HEADER_rtmodel_h_ */

4
clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/OpREDHAWKtarget/rtw_proj.tmw
View file

@ -1,4 +0,0 @@
Simulink Coder project for asyncip_sl_1_sm_ip_test using C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tmf. MATLAB root = C:\Program Files (x86)\MATLAB\R2011b. SimStruct date: 11-Jul-2011 20:59:52
This file is generated by Simulink Coder for use by the make utility
to determine when to rebuild objects when the name of the current Simulink Coder project changes.
The rtwinfomat located at: ..\slprj\rtlab_rtmodel\asyncip_sl_1_sm_ip_test\tmwinternal\binfo.mat

1191
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648
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@ -1,648 +0,0 @@
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clients/opal/models/AsyncIP_sl/AsyncIP_sl_sm_ip_test/slprj/sl_proj.tmw
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@ -1,2 +0,0 @@
Simulink Coder project marker file. Please don't change it.
slprjVersion: 7.8_30

2
clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.Comm
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@ -1,2 +0,0 @@
AsyncIP_sl/sc_console/OpComm: 1,1,1 : 0.000000000000000 : 0.000000000000000, 0.000000000000000, 0.000000000000000 : 1 : 0 : [0,0,0]
SampleTime=0.000050000000000

2
clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.acqgr
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@ -1,2 +0,0 @@
2
1 0.000050000 1 13

3
clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.alias
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@ -1,3 +0,0 @@
[General]
aliascnt=0
[Alias]

19
clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.param
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@ -1,19 +0,0 @@
[General]
ATT_VERSION=1
[Size]
nbParameters=13
nbValues=13
nbVariables=0
nbParamsVar=0
[Parameter]
0=AsyncIP_sl/sm_ip_test/data ready 1 kHz|Amplitude| |Scalar|1|1|2|1.0|1|1|
1=AsyncIP_sl/sm_ip_test/data ready 1 kHz|Period| |Scalar|1|1|3|2.0|1|1|
2=AsyncIP_sl/sm_ip_test/data ready 1 kHz|PulseWidth| |Scalar|1|1|4|1.0|1|1|
3=AsyncIP_sl/sm_ip_test/data ready 1 kHz|PhaseDelay| |Scalar|1|1|5|0.0|1|1|
4=AsyncIP_sl/sm_ip_test/constants|Value| |RVector|1|4|6|1.0|2.0|3.0|4.0|1|4|
8=AsyncIP_sl/sm_ip_test/Pulse Generator|Amplitude| |Scalar|1|1|10|5.0|1|1|
9=AsyncIP_sl/sm_ip_test/Pulse Generator|Period| |Scalar|1|1|11|2000.0|1|1|
10=AsyncIP_sl/sm_ip_test/Pulse Generator|PulseWidth| |Scalar|1|1|12|600.0|1|1|
11=AsyncIP_sl/sm_ip_test/Pulse Generator|PhaseDelay| |Scalar|1|1|13|0.0|1|1|
12=AsyncIP_sl/sm_ip_test/timeout|Value| |Scalar|1|1|83|2.0|1|1|
[Variable]

16
clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.sig
View file

@ -1,16 +0,0 @@
[AcqGr1]
1=AsyncIP_sl/sm_ip_test/port2(1)|signal1.signal1|1|1
2=AsyncIP_sl/sm_ip_test/port2(2)|signal1.signal2|1|2
3=AsyncIP_sl/sm_ip_test/port2(3)|signal1.signal3|1|3
4=AsyncIP_sl/sm_ip_test/port1(1)|signal1(1)|2|1
5=AsyncIP_sl/sm_ip_test/port1(2)|signal1(2)|2|2
6=AsyncIP_sl/sm_ip_test/port1(3)|signal1(3)|2|3
7=AsyncIP_sl/sm_ip_test/port1(4)|signal1(4)|2|4
8=AsyncIP_sl/sm_ip_test/port1(5)|signal1(5)|2|5
9=AsyncIP_sl/sm_ip_test/port3(1)|signal1.signal1(1)|3|1
10=AsyncIP_sl/sm_ip_test/port3(2)|signal1.signal1(2)|3|2
11=AsyncIP_sl/sm_ip_test/port3(3)|signal1.signal1(3)|3|3
12=AsyncIP_sl/sm_ip_test/port3(4)|signal1.signal1(4)|3|4
13=AsyncIP_sl/sm_ip_test/port3(5)|signal1.signal2|3|5
nbsignals=13

29
clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.signal
View file

@ -1,29 +0,0 @@
[Size]
nbSignals=10
nbFixedSignals=13
nbControlSignal=0
[Signal]
1=AsyncIP_sl/sm_ip_test/data ready 1 kHz/port1|signal1|1|1|2|1|1|1|S|
2=AsyncIP_sl/sm_ip_test/Pulse Generator/port1|signal1|1|1|3|1|1|1|S|
3=AsyncIP_sl/sm_ip_test/send message 1/S-Function2/port1|signal1|1|1|4|1|1|1|S|
4=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port1|signal1|1|1|5|1|1|1|S|
5=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port2|signal2|1|2|6|1|1|1|S|
6=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(1)|signal3(1)|1|3|7|1|5|1|V|
7=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(2)|signal3(2)|1|3|8|1|5|1|V|
8=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(3)|signal3(3)|1|3|9|1|5|1|V|
9=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(4)|signal3(4)|1|3|10|1|5|1|V|
10=AsyncIP_sl/sm_ip_test/receive message 1/S-Function1/port3(5)|signal3(5)|1|3|11|1|5|1|V|
[FixedSignal]
1=AsyncIP_sl/sm_ip_test/port2(1)|signal1.signal1|1|1|0|1|
2=AsyncIP_sl/sm_ip_test/port2(2)|signal1.signal2|1|1|0|1|
3=AsyncIP_sl/sm_ip_test/port2(3)|signal1.signal3|1|1|0|1|
4=AsyncIP_sl/sm_ip_test/port1(1)|signal1(1)|1|1|0|1|
5=AsyncIP_sl/sm_ip_test/port1(2)|signal1(2)|1|1|0|1|
6=AsyncIP_sl/sm_ip_test/port1(3)|signal1(3)|1|1|0|1|
7=AsyncIP_sl/sm_ip_test/port1(4)|signal1(4)|1|1|0|1|
8=AsyncIP_sl/sm_ip_test/port1(5)|signal1(5)|1|1|0|1|
9=AsyncIP_sl/sm_ip_test/port3(1)|signal1.signal1(1)|1|1|0|1|
10=AsyncIP_sl/sm_ip_test/port3(2)|signal1.signal1(2)|1|1|0|1|
11=AsyncIP_sl/sm_ip_test/port3(3)|signal1.signal1(3)|1|1|0|1|
12=AsyncIP_sl/sm_ip_test/port3(4)|signal1.signal1(4)|1|1|0|1|
13=AsyncIP_sl/sm_ip_test/port3(5)|signal1.signal2|1|1|0|1|

2
clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl.subsys
View file

@ -1,2 +0,0 @@
AsyncIP_sl/sm_ip_test,asyncip_sl_1_sm_ip_test,1
AsyncIP_sl/sc_console,asyncip_sl_2_sc_console,2

206
clients/opal/models/AsyncIP_sl/Opcommon/AsyncIP_sl_OpREDHAWKtarget_Compilation.log
View file

@ -1,206 +0,0 @@
-------------------- Starting compilation --------------------
Start at : Wednesday, May 28, 2014, 12:53:31
The current RT-LAB version is: v10.5.9.356
The current model is: D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl.mdl
The current host platform is: XP/Vista/7
The current target platform is: Redhat
The current compiler is: Automatic
Preparing original model for code separation and generation...
The current Matlab version is: v7.13 (32 Bit)
Diagnostics:
Reported by: RT-LAB
Source : AsyncIP_sl
Message : Warning: Block Reduction Optimization is set to ON. Real Time Workshop will optimize and remove some
unused blocks in the model. Those signals might not be visible with Rt-Lab Dynamic Acquisition after
compilation. This option can be changed in the Simulink model : Simulation/Configuration Parameters/Optimization
RtlabInfo not loaded
Separating RT-LAB model (number of RT subsystems = 1, console detected).
Separating RT-LAB subsystem 'sm_ip_test'.
WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
Separating RT-LAB subsystem 'sc_console'.
WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
WARNING: Saving subsystems with breaklinks option has been disabled. Subsystems real-time behavior may be different.
Model preparation and separation duration : 00h:00m:07s
-------------------- Completed successfully --------------------
-------------------- Generating C code --------------------
Using System Target File (TLC file) : rtlab_rtmodel.tlc...
Using Template Makefile (TMF file) : rtlab_rtmodel.tmf...
-------------------- Generating asyncip_sl_1_sm_ip_test C code --------------------
Calling RTW Make Command make_rtw...
### Starting build procedure for model: asyncip_sl_1_sm_ip_test
### Generating code into build folder: D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\asyncip_sl_1_sm_ip_test_rtlab
### Invoking Target Language Compiler on asyncip_sl_1_sm_ip_test.rtw
### Using System Target File: C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tlc
### Loading TLC function libraries
.....
### Initial pass through model to cache user defined code
.....
### Caching model source code
...................................................................
### Writing header file asyncip_sl_1_sm_ip_test.h
### Writing header file asyncip_sl_1_sm_ip_test_types.h
.
### Writing header file rtwtypes.h
### Writing source file asyncip_sl_1_sm_ip_test.c
### Writing header file asyncip_sl_1_sm_ip_test_private.h
.
### Writing header file rtmodel.h
### Writing source file asyncip_sl_1_sm_ip_test_data.c
### Writing header file rt_nonfinite.h
.
### Writing source file rt_nonfinite.c
### Writing header file rt_defines.h
.
### Writing header file rtGetInf.h
### Writing source file rtGetInf.c
### Writing header file rtGetNaN.h
.
### Writing source file rtGetNaN.c
### TLC code generation complete.
### Creating model mapping file asyncip_sl_1_sm_ip_test.map using map_r2011a.tlc
...............................### Creating project marker file: rtw_proj.tmw
.
### Processing Template Makefile: C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tmf
### Wrapping unrecognized make command (angle brackets added)
### <make>
### in default batch file
### Creating asyncip_sl_1_sm_ip_test.mk from C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink\rtw\c\common\rtlab_rtmodel.tmf
### Successful completion of code generation for model: asyncip_sl_1_sm_ip_test
asyncip_sl_1_sm_ip_test : Generating C code duration : 00h:00m:06s
Generating C code total duration : 00h:00m:06s
-------------------- Completed successfully --------------------
-------------------- Creating the parameter database --------------------
Parameter(s) with more than 20 values will be disabled.
Use PARAM_VECTOR_SIZE_LIMIT environment variable to modify this limit.
Parameter database creation duration: 00h:00m:00s
-------------------- Parameter database created successfully --------------------
-------------------- Creating the signals database --------------------
Signal(s) with more than 20 values will be disabled.
Use SIGNALS_VECTOR_SIZE_LIMIT environment variable to modify this limit.
Signal database creation duration: 00h:00m:00s
-------------------- Signal database created successfully --------------------
-------------------- Transferring the generated C code --------------------
Connecting to 137.226.160.69 ... OK.
Setting remote directory to /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/... OK.
Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink/rtw/c/common/linux32.opt ... OK.
Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\Simulink/rtw/c/common/posix.rules ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\target_precompile.py ... Failed.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test*.c ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test*.h ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rtGet* ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test.mk ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test.prm ... Failed.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\asyncip_sl_1_sm_ip_test.reg ... Failed.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rt_*.* ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rtwtypes.* ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\rtmodel.h ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\drive_asyncip_sl_1_sm_ip_test*.c ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\drive_asyncip_sl_1_sm_ip_test*.h ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\OpREDHAWKtarget\Opal*.c ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\slprj\rtlab_rtmodel\_sharedutils\*.c ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\slprj\rtlab_rtmodel\_sharedutils\*.h ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP_sl_sm_ip_test\slprj\rtlab_rtmodel\_sharedutils\*.mk ... OK.
Transferring common RT-LAB files:
Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\include_target\*.h ... OK.
Transferring in ascii mode C:\OPAL-RT\RT-LAB\v10.5.9.356\simulink\rtw\c\common\model_main.c ... OK.
Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalCore.a ... OK.
Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalUtils_redhawk.a ... OK.
Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalUtils.a ... OK.
Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalOhci.a ... OK.
Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libirc.a ... OK.
Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libimf.a ... OK.
Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\simulink\libR2011b\redhawk\libOpalRTE*.a ... OK.
Transferring user extra files:
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP.c ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIP.mk ... OK.
Transferring in ascii mode D:\msv\svo\opal\test_s2ss_to_opal\models\AsyncIP_sl\AsyncIPUtils.h ... OK.
Transferring in binary mode C:\OPAL-RT\RT-LAB\v10.5.9.356\common\lib\redhawk\libOpalAsyncApiCore.a ... OK.
File transfer duration : 00h:00m:02s
-------------------- Completed successfully --------------------
-------------------- Building the generated C code --------------------
Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_precompile.py ... done
Removing relative includes from ./../asyncip_sl_sm_ip_test/model_main.c ... Done
Executing script /usr/opalrt/v10.5.9.356/common/python/rtlab/global/target_subsys_precompile.py ... done
-------------------- Building asyncip_sl_1_sm_ip_test --------------------
/usr/bin/make -f AsyncIP.mk
make[1]: Entering directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
opicc -c -O -D_GNU_SOURCE -I. -c -o AsyncIP.o AsyncIP.c
AsyncIP.c(167): warning #167: argument of type "int *" is incompatible with parameter of type "unsigned int *"
if((n = OpalWaitForAsyncSendRequest (&SendID)) != EOK)
^
opicpc -L. -o AsyncIP AsyncIP.o -lOpalAsyncApiCore -lOpalCore -lOpalUtils -lpthread -lm -ldl -lutil -lrt
chmod 777 AsyncIP
### Created executable: AsyncIP
make[1]: Leaving directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
/usr/bin/make -f asyncip_sl_1_sm_ip_test.mk
make[1]: Entering directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
rm -f asyncip_sl_1_sm_ip_test
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils asyncip_sl_1_sm_ip_test.c
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils model_main.c
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_sim.c
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils asyncip_sl_1_sm_ip_test_data.c
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils rtGetInf.c
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils rtGetNaN.c
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_logging.c
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_matrx.c
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils rt_nonfinite.c
opicc -c -O2 -xHost -falign-functions=2 -diag-disable remark,warn,cpu-dispatch -DUSE_RTMODEL -DMODEL=asyncip_sl_1_sm_ip_test -DRT=RT -DNUMST=2 -DTID01EQ=0 -DNCSTATES=0 -DMULTITASKING=0 -D_SIMULINK -DRTLAB -DOP_MATLABR2011B -DUNIX -I/usr/opalrt/externals/include -I. -I/usr/matlab/v7.13/simulink/include -I/usr/matlab/v7.13/extern/include -I/usr/matlab/v7.13/rtw/c/src -I/usr/matlab/v7.13/rtw/c/src/matrixmath -I/usr/matlab/v7.13/rtw/c/libsrc -I/usr/matlab/v7.13/toolbox/simscape/include/drive -I/usr/matlab/v7.13/toolbox/simscape/include/mech -I/usr/matlab/v7.13/toolbox/simscape/include/foundation -I/usr/matlab/v7.13/toolbox/simscape/include/network_engine -I/usr/matlab/v7.13/toolbox/simscape/include/ne_sli -I/usr/matlab/v7.13/toolbox/dspblks/include -I/usr/opalrt/v10.5.9.356/common/include -I/usr/opalrt/v10.5.9.356/common/include_target -I/usr/opalrt/v10.5.9.356/RT-LAB/include -I_sharedutils /usr/matlab/v7.13/rtw/c/src/rt_printf.c
### Linking ...
opicpc -Wl,-rpath=/usr/opalrt/v10.5.9.356/common/bin -Wl,-rpath='/opt/intel/Compiler/11.1/072/lib/ia32' -Wl,-rpath='/opt/intel/Compiler/11.1/056/lib/ia32' -diag-disable remark -L. -L/usr/opalrt/v10.5.9.356/RT-LAB/lib -L/usr/opalrt/v10.5.9.356/common/lib -L/usr/opalrt/v10.5.9.356/common/lib/redhawk -L/usr/opalrt/v10.5.9.356/common/bin -L/usr/opalrt/externals/lib -L/usr/matlab/v7.13/toolbox/dspblks/lib/redhawk -L/usr/matlab/v7.13/toolbox/simscape/lib/redhawk -o asyncip_sl_1_sm_ip_test asyncip_sl_1_sm_ip_test.o model_main.o rt_sim.o asyncip_sl_1_sm_ip_test_data.o rtGetInf.o rtGetNaN.o rt_logging.o rt_matrx.o rt_nonfinite.o rt_printf.o -lOpalAsyncApiR2011b -lOpalAsyncApiCore -lOpalSfunR2011b -lOpalR2011b -lBlocksRT-2011b -lOpalCore -lOpalOhci -lOpalCore -llicenseRH32 -lSystem -lPlatform -lFramework -lMatio -lOpal -lInfrastructure -lNumeric -lSimulink -lNetwork -lOpalUtils -ldspblks -lsimscape -lpthread -lm -ldl -lutil -lrt /usr/matlab/v7.13/rtw/c/libsrc/rtwlibr_redhawk.a
chmod a+x asyncip_sl_1_sm_ip_test
### Created executable: asyncip_sl_1_sm_ip_test
make[1]: Leaving directory `/home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test'
asyncip_sl_1_sm_ip_test : Building subsystem duration : 00h:00m:01s
Building model total duration : 00h:00m:01s
-------------------- Completed successfully --------------------
-------------------- Transferring the built model --------------------
Connecting to 137.226.160.69 ... OK.
Transferring in binary mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/asyncip_sl_1_sm_ip_test ... OK.
Transferring in ascii mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/compilation_target_report.xml ... OK.
Transferring in binary mode /home/acs/d/msv/svo/opal/test_s2ss_to_opal/models/asyncip_sl/asyncip_sl_sm_ip_test/AsyncIP ... OK.
File transfer duration : 00h:00m:01s
-------------------- Completed successfully --------------------
End at : Wednesday, May 28, 2014, 12:53:50
Compilation duration : 00h:00m:19s

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3184
clients/opal/models/AsyncIP_sl/report/temp/host_report.xml
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File diff suppressed because it is too large Load diff

648
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View file

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301
clients/opal/models/AsyncIP_sl/report/tree/tree.js
View file

@ -1,301 +0,0 @@
var platformMoz = (document.implementation && document.implementation.createDocument);
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cache = new ActiveXObject('Msxml2.XSLTemplate.' + msxmlVersion);
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function initializeTree(defTreeMode)
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if (noXSLT)
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alert("Sorry, this doesn't work in your browser");
return;
}
urlXML = get_report_filename()
urlXSL = "tree/tree.xsl";
target = document.getElementById("xmlContent");
DefaultTreeMode = defTreeMode;
Transform();
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function get_report_filename()
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var filename;
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var j;
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return 'xml/' + filename.substring(i+1,j) + '.xml'
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docXSL.load(urlXSL);
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processor = new XSLTProcessor();
processor.importStylesheet(docXSL);
processor.setParameter(null, "DefaultTreeMode", DefaultTreeMode);
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cache.stylesheet = docXSL;
processor = cache.createProcessor();
processor.input = docXML;
processor.addParameter("DefaultTreeMode", DefaultTreeMode);
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//----------------------------------------------------
function cancelBuble(event)
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entity.setAttribute("open","true")
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entity.setAttribute("open","false")
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function expandAllFromString(entityString)
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var i
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249
clients/opal/models/AsyncIP_sl/report/tree/tree.xsl
View file

@ -1,249 +0,0 @@
<?xml version="1.0" encoding="ISO-8859-1"?>
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<xsl:output method="html" indent="yes" encoding="iso-8859-1"/>
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<xsl:param name="DefaultTreeMode" select="'expand'"/>
<!-- _____ ITEM ________________________________________-->
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<h1>RT-LAB Report</h1>
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clients/opal/models/AsyncIP_sl/report/xml/AsyncIP_sl.xml
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21
clients/opal/models/AsyncIP_sl/report/xml/report.xml
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@ -1,21 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<item name="report">
<item name="general">
<property name="User">
<value>
UserName
</value>
</property>
<property name="Command station">
<value>
ComputerName
</value>
</property>
<property name="Date">
<value>
CurrentDate
</value>
</property>
</item>
</item>