update Steffens mail address

Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2025-03-09 00:00:00 +01:00 · 2022-12-14 17:44:17 +01:00 · 2022-12-14 17:44:17 +01:00 · dee5b2d81f
commit dee5b2d81f
parent d855198de7
40 changed files with 42 additions and 42 deletions
--- a/fpga/Dockerfile
+++ b/fpga/Dockerfile
@ -8,7 +8,7 @@
 # by running:
 #   make docker
 #
-# @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+# @author Steffen Vogel <post@steffenvogel.de>
 # @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 # @license GNU General Public License (version 3)
 #
@ -36,7 +36,7 @@ LABEL \
 	org.label-schema.license="GPL-3.0" \
 	org.label-schema.vendor="Institute for Automation of Complex Power Systems, RWTH Aachen University" \
 	org.label-schema.author.name="Steffen Vogel" \
-	org.label-schema.author.email="stvogel@eonerc.rwth-aachen.de" \
+	org.label-schema.author.email="post@steffenvogel.de" \
 	org.label-schema.description="A image containing all build-time dependencies for VILLASfpga based on Fedora" \
 	org.label-schema.url="http://fein-aachen.org/projects/villas-framework/" \
 	org.label-schema.vcs-url="https://git.rwth-aachen.de/VILLASframework/VILLASfpga" \
--- a/fpga/README.md
+++ b/fpga/README.md
@ -12,7 +12,7 @@ User documentation is available here: <https://villas.fein-aachen.org/doc/fpga.h
 ## Copyright

 - 2022 Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
- 2018-2022 Steffen Vogel <svogel2@eonerc.rwth-aachen.de>
+- 2018-2022 Steffen Vogel <post@steffenvogel.de>
 - 2018 Daniel Krebs <dkrebs@eonerc.rwth-aachen.de>

 ## License
@ -46,7 +46,7 @@ For other licensing options please consult [Prof. Antonello Monti](mailto:amonti
 [![EONERC ACS Logo](doc/pictures/eonerc_logo.png)](http://www.acs.eonerc.rwth-aachen.de)

 - Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
- Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+- Steffen Vogel <post@steffenvogel.de>
 - Daniel Krebs <dkrebs@eonerc.rwth-aachen.de>

 [Institute for Automation of Complex Power Systems (ACS)](http://www.acs.eonerc.rwth-aachen.de)
--- a/fpga/include/villas/fpga/card.hpp
+++ b/fpga/include/villas/fpga/card.hpp
@ -3,7 +3,7 @@
 * This class represents a FPGA device.
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 * @license GNU General Public License (version 3)
--- a/fpga/include/villas/fpga/config.h
+++ b/fpga/include/villas/fpga/config.h
@ -4,7 +4,7 @@
 * This settings are not part of the configuration file.
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 * @license GNU General Public License (version 3)
 *
--- a/fpga/include/villas/fpga/core.hpp
+++ b/fpga/include/villas/fpga/core.hpp
@ -3,7 +3,7 @@
 * This class represents a module within the FPGA.
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 * @license GNU General Public License (version 3)
--- a/fpga/include/villas/fpga/ips/dma.hpp
+++ b/fpga/include/villas/fpga/ips/dma.hpp
@ -1,7 +1,7 @@
 /** DMA driver
 *
 * @author Daniel Krebs <github@daniel-krebs.net>
- * @author Steffen Vogel <svogel2@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 * @copyright 2018-2022, Institute for Automation of Complex Power Systems, EONERC
 * @license GNU General Public License (version 3)
--- a/fpga/include/villas/fpga/ips/emc.hpp
+++ b/fpga/include/villas/fpga/ips/emc.hpp
@ -1,7 +1,7 @@
 /** AXI External Memory Controller (EMC)
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2020, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/include/villas/fpga/ips/fifo.hpp
+++ b/fpga/include/villas/fpga/ips/fifo.hpp
@ -2,7 +2,7 @@
 *
 * These functions present a simpler interface to Xilinx' Timer Counter driver (XTmrCtr_*)
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
--- a/fpga/include/villas/fpga/ips/gpio.hpp
+++ b/fpga/include/villas/fpga/ips/gpio.hpp
@ -1,7 +1,7 @@
 /** AXI General Purpose IO (GPIO)
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2020, Steffen Vogel
 * @license GNU General Public License (version 3)
--- a/fpga/include/villas/fpga/ips/intc.hpp
+++ b/fpga/include/villas/fpga/ips/intc.hpp
@ -1,7 +1,7 @@
 /** AXI-PCIe Interrupt controller
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
--- a/fpga/include/villas/fpga/ips/pcie.hpp
+++ b/fpga/include/villas/fpga/ips/pcie.hpp
@ -3,7 +3,7 @@
 * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
--- a/fpga/include/villas/fpga/ips/rtds.hpp
+++ b/fpga/include/villas/fpga/ips/rtds.hpp
@ -1,7 +1,7 @@
 /** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/include/villas/fpga/ips/switch.hpp
+++ b/fpga/include/villas/fpga/ips/switch.hpp
@ -3,7 +3,7 @@
 * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
--- a/fpga/include/villas/fpga/ips/timer.hpp
+++ b/fpga/include/villas/fpga/ips/timer.hpp
@ -2,7 +2,7 @@
 *
 * These functions present a simpler interface to Xilinx' Timer Counter driver (XTmrCtr_*)
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
--- a/fpga/include/villas/fpga/node.hpp
+++ b/fpga/include/villas/fpga/node.hpp
@ -3,7 +3,7 @@
 * This class represents a module within the FPGA.
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 * @license GNU General Public License (version 3)
--- a/fpga/lib/card.cpp
+++ b/fpga/lib/card.cpp
@ -1,6 +1,6 @@
 /** FPGA card.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 * @license GNU General Public License (version 3)
 *
--- a/fpga/lib/core.cpp
+++ b/fpga/lib/core.cpp
@ -1,6 +1,6 @@
 /** FPGA IP component.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 * @license GNU General Public License (version 3)
 *
--- a/fpga/lib/ips/emc.cpp
+++ b/fpga/lib/ips/emc.cpp
@ -1,6 +1,6 @@
 /** AXI External Memory Controller (EMC)
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2020, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/lib/ips/fifo.cpp
+++ b/fpga/lib/ips/fifo.cpp
@ -2,7 +2,7 @@
 *
 * These functions present a simpler interface to Xilinx' FIFO driver (XLlFifo_*)
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
--- a/fpga/lib/ips/gpio.cpp
+++ b/fpga/lib/ips/gpio.cpp
@ -1,6 +1,6 @@
 /** AXI General Purpose IO (GPIO)
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2020, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/lib/ips/intc.cpp
+++ b/fpga/lib/ips/intc.cpp
@ -1,6 +1,6 @@
 /** AXI-PCIe Interrupt controller
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/lib/ips/rtds.cpp
+++ b/fpga/lib/ips/rtds.cpp
@ -1,6 +1,6 @@
 /** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/lib/ips/switch.cpp
+++ b/fpga/lib/ips/switch.cpp
@ -2,7 +2,7 @@
 *
 * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
--- a/fpga/lib/ips/timer.cpp
+++ b/fpga/lib/ips/timer.cpp
@ -2,7 +2,7 @@
 *
 * These functions present a simpler interface to Xilinx' Timer Counter driver (XTmrCtr_*)
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
--- a/fpga/lib/vlnv.cpp
+++ b/fpga/lib/vlnv.cpp
@ -1,6 +1,6 @@
 /** Vendor, Library, Name, Version (VLNV) tag
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 * @license GNU General Public License (version 3)
 *
--- a/fpga/past-commits.txt
+++ b/fpga/past-commits.txt
@ -22,7 +22,7 @@ a4120eda2d327aa537fa874885c200c858202fcc ips/dma: acknowledge interrupts in DMA

 ---

-I, Steffen Vogel hereby sign-off-by all of my past commits to this repo subject to the Developer Certificate of Origin (DCO), Version 1.1. In the past I have used emails: post@steffenvogel.de, stvogel@eonerc.rwth-aachen.de
+I, Steffen Vogel hereby sign-off-by all of my past commits to this repo subject to the Developer Certificate of Origin (DCO), Version 1.1. In the past I have used emails: post@steffenvogel.de, post@steffenvogel.de

 e256a94957294714d6bf645fa9c9f17253fa154e Merge branch 'fix-dockerfile' into 'master'
 44fcb85aebeedc531b061d41c847eabbc8cee478 minor code-style fixes
--- a/fpga/scripts/non_root.sh
+++ b/fpga/scripts/non_root.sh
@ -2,7 +2,7 @@
 #
 # Setup VFIO for non-root users
 #
-# @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+# @author Steffen Vogel <post@steffenvogel.de>
 # @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 # @license GNU General Public License (version 3)
 #
--- a/fpga/scripts/rebind_device.sh
+++ b/fpga/scripts/rebind_device.sh
@ -2,7 +2,7 @@
 #
 # Detach and rebind a PCI device to a PCI kernel driver
 #
-# @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+# @author Steffen Vogel <post@steffenvogel.de>
 # @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 # @license GNU General Public License (version 3)
 #
--- a/fpga/scripts/reset_pci_device.sh
+++ b/fpga/scripts/reset_pci_device.sh
@ -2,7 +2,7 @@
 #
 # Reset PCI devices like FPGAs after a reflash
 #
-# @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+# @author Steffen Vogel <post@steffenvogel.de>
 # @copyright 2017-2022, Institute for Automation of Complex Power Systems, EONERC
 # @license GNU General Public License (version 3)
 #
--- a/fpga/tests/unit/dma.cpp
+++ b/fpga/tests/unit/dma.cpp
@ -1,6 +1,6 @@
 /** DMA unit test.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/tests/unit/fifo.cpp
+++ b/fpga/tests/unit/fifo.cpp
@ -1,6 +1,6 @@
 /** FIFO unit test.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/tests/unit/fpga.cpp
+++ b/fpga/tests/unit/fpga.cpp
@ -1,6 +1,6 @@
 /** FPGA related code for bootstrapping the unit-tests
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2018-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/tests/unit/global.hpp
+++ b/fpga/tests/unit/global.hpp
@ -1,6 +1,6 @@
 /** Global include for tests.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/tests/unit/gpu.cpp
+++ b/fpga/tests/unit/gpu.cpp
@ -1,6 +1,6 @@
 /** GPU unit tests.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/tests/unit/logging.cpp
+++ b/fpga/tests/unit/logging.cpp
@ -1,6 +1,6 @@
 /** Logging utilities for unit test.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/tests/unit/main.cpp
+++ b/fpga/tests/unit/main.cpp
@ -1,6 +1,6 @@
 /** Main Unit Test entry point.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/tests/unit/rtds.cpp
+++ b/fpga/tests/unit/rtds.cpp
@ -1,6 +1,6 @@
 /** RTDS AXI-Stream RTT unit test.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2018-2022, Steffen Vogel, Daniel Krebs
 * @license GNU General Public License (version 3)
--- a/fpga/tests/unit/rtds2gpu.cpp
+++ b/fpga/tests/unit/rtds2gpu.cpp
@ -1,7 +1,7 @@
 /** FIFO unit test.
 *
 * @file
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/tests/unit/rtds_rtt.cpp
+++ b/fpga/tests/unit/rtds_rtt.cpp
@ -1,6 +1,6 @@
 /** RTDS AXI-Stream RTT unit test.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
--- a/fpga/tests/unit/timer.cpp
+++ b/fpga/tests/unit/timer.cpp
@ -1,6 +1,6 @@
 /** Timer/Counter unit test.
 *
- * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
+ * @author Steffen Vogel <post@steffenvogel.de>
 * @copyright 2017-2022, Steffen Vogel
 * @license GNU General Public License (version 3)
 *