1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-09 00:00:00 +01:00

lib/ips/timer: implement basic functionality

This commit is contained in:
daniel-k 2018-01-16 15:05:37 +01:00
parent 05131258d4
commit e05ff515c7
2 changed files with 51 additions and 4 deletions

View file

@ -29,9 +29,13 @@
#pragma once
#include "fpga/ip.hpp"
#include <stdint.h>
#include <xilinx/xtmrctr.h>
#include "config.h"
#include "fpga/ip.hpp"
#include "fpga/ips/intc.hpp"
namespace villas {
namespace fpga {
namespace ip {
@ -42,8 +46,24 @@ class Timer : public IpCore
public:
bool init();
bool start(uint32_t ticks);
bool wait();
uint32_t remaining();
inline bool isRunning()
{ return remaining() != 0; }
inline bool isFinished()
{ return remaining() == 0; }
static constexpr uint32_t
getFrequency()
{ return FPGA_AXI_HZ; }
private:
XTmrCtr xTmr;
InterruptController* intc;
};

View file

@ -23,11 +23,11 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
#include "config.h"
#include <xilinx/xtmrctr.h>
#include "log.hpp"
#include "fpga/ips/timer.hpp"
#include "fpga/ips/intc.hpp"
namespace villas {
namespace fpga {
@ -40,14 +40,41 @@ static TimerFactory factory;
bool Timer::init()
{
XTmrCtr_Config xtmr_cfg;
xtmr_cfg.SysClockFreqHz = FPGA_AXI_HZ;
xtmr_cfg.SysClockFreqHz = getFrequency();
XTmrCtr_CfgInitialize(&xTmr, &xtmr_cfg, getBaseaddr());
XTmrCtr_InitHw(&xTmr);
intc = reinterpret_cast<InterruptController*>(dependencies["intc"]);
intc->disableInterrupt(irqs[0]);
return true;
}
bool Timer::start(uint32_t ticks)
{
intc->enableInterrupt(irqs[0], false);
XTmrCtr_SetOptions(&xTmr, 0, XTC_EXT_COMPARE_OPTION | XTC_DOWN_COUNT_OPTION);
XTmrCtr_SetResetValue(&xTmr, 0, ticks);
XTmrCtr_Start(&xTmr, 0);
return true;
}
bool Timer::wait()
{
int count = intc->waitForInterrupt(irqs[0]);
intc->disableInterrupt(irqs[0]);
return (count == 1);
}
uint32_t Timer::remaining()
{
return XTmrCtr_GetValue(&xTmr, 0);
}
} // namespace ip
} // namespace fpga