lib/ip: change interface: start() -> init()

fpga/include/villas/fpga/card.hpp

@@ -67,7 +67,7 @@ public:
 
 	PCIeCard() : filter(PCI_FILTER_DEFAULT_FPGA) {}
 
-	bool start();
+	bool init();
 	bool stop()  { return true; }
 	bool check() { return true; }
 	bool reset() { return true; }

fpga/include/villas/fpga/ip.hpp

@@ -81,7 +81,7 @@ public:
 
 	// IPs can implement this interface
 	virtual bool check() { return true; }
-	virtual bool start() { return true; }
+	virtual bool init() { return true; }
 	virtual bool stop()  { return true; }
 	virtual bool reset() { return true; }
 	virtual void dump();

fpga/include/villas/fpga/ips/fifo.hpp

@@ -43,7 +43,7 @@ class Fifo : public IpNode
 public:
 	friend class FifoFactory;
 
-	bool start();
+	bool init();
 	bool stop();
 
 	size_t write(const void* buf, size_t len);

fpga/include/villas/fpga/ips/intc.hpp

@@ -46,7 +46,7 @@ public:
 
 	~InterruptController();
 
-	bool start();
+	bool init();
 
 	int enableInterrupt(IrqMaskType mask, bool polling);
 	int enableInterrupt(IrqPort irq, bool polling)

fpga/include/villas/fpga/ips/switch.hpp

@@ -47,7 +47,7 @@ class AxiStreamSwitch : public IpNode {
 public:
 	friend class AxiStreamSwitchFactory;
 
-	bool start();
+	bool init();
 
 	bool connect(int portSlave, int portMaster);
 	bool disconnectMaster(int port);

fpga/include/villas/fpga/ips/timer.hpp

@@ -40,7 +40,7 @@ namespace ip {
 class Timer : public IpCore
 {
 public:
-	bool start();
+	bool init();
 
 private:
 	XTmrCtr xTmr;

fpga/lib/card.cpp

@@ -102,10 +102,10 @@ fpga::PCIeCardFactory::make(json_t *json, struct pci* pci, ::vfio_container* vc)
 
 
 		// TODO: currently fails, fix and remove comment
-//		if(not card->start()) {
-//		    logger->warn("Cannot start FPGA card {}", card_name);
-//			continue;
-//		}
+		if(not card->init()) {
+			logger->warn("Cannot start FPGA card {}", card_name);
+			continue;
+		}
 
 		card->ips = ip::IpCoreFactory::make(card.get(), json_ips);
 		if(card->ips.empty()) {
@@ -142,7 +142,7 @@ PCIeCard::lookupIp(std::string name) const {
 }
 
 
-bool fpga::PCIeCard::start()
+bool fpga::PCIeCard::init()
 {
 	int ret;
 	struct pci_device *pdev;

fpga/lib/ip.cpp

@@ -284,10 +284,10 @@ IpCoreFactory::make(PCIeCard* card, json_t *json_ips)
 		}
 
 		// TODO: currently fails, fix and remove comment
-//		if(not ip->start()) {
-//			logger->error("Cannot start IP {}", ip->id.name);
-//			continue;
-//		}
+		if(not ip->init()) {
+			logger->error("Cannot start IP {}", ip->id.name);
+			continue;
+		}
 
 		if(not ip->check()) {
 			logger->error("Checking of IP {} failed", ip->id.name);

fpga/lib/ips/fifo.cpp

@@ -60,7 +60,7 @@ FifoFactory::configureJson(IpCore &ip, json_t *json_ip)
 }
 
 
-bool Fifo::start()
+bool Fifo::init()
 {
 	XLlFifo_Config fifo_cfg;
 

fpga/lib/ips/intc.cpp

@@ -45,7 +45,7 @@ InterruptController::~InterruptController()
 	vfio_pci_msi_deinit(&card->vfio_device , this->efds);
 }
 
-bool InterruptController::start()
+bool InterruptController::init()
 {
 	const uintptr_t base = getBaseaddr();
 

fpga/lib/ips/switch.cpp

@@ -35,7 +35,7 @@ namespace ip {
 static AxiStreamSwitchFactory factory;
 
 bool
-AxiStreamSwitch::start()
+AxiStreamSwitch::init()
 {
 	/* Setup AXI-stream switch */
 	XAxis_Switch_Config sw_cfg;

fpga/lib/ips/timer.cpp

@@ -37,7 +37,7 @@ namespace ip {
 // instantiate factory to make available to plugin infrastructure
 static TimerFactory factory;
 
-bool Timer::start()
+bool Timer::init()
 {
 	XTmrCtr_Config xtmr_cfg;
 	xtmr_cfg.SysClockFreqHz = FPGA_AXI_HZ;