Niklas Eiling
21221eb698
fpga: fix empty search path being an error
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
61ab82dbb7
Fix missing idle_stop setting in integration tests
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
61e74b3e73
Revert default sample length to 64
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
10eb88e7c8
test_rtt: Disable integration test in CI
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
cc44595f98
test_rtt: Fix possible use of uninitialized variable
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
63337efdd7
test_rtt: Add missing cooldown phase in runtime estimation
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
722280f968
Increase default sample length
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
c10fcc5bd4
test_rtt: Fix logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
aee96e846f
webrtc: Improve logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
b0680bb5cf
test_rtt: Fix compiler errors
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
54d7cf0620
webrtc: Show connection details
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
2e00453f7b
test_rtt: Improve handling of defaults
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
c4afbf5453
test_rtt: Print estimated test durations
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
f6c7434a61
test_rtt: Rework calculation of test duration
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
64749223e8
test_rtt: Improve statistics
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
139101c447
webrtc: Enable ICE TCP
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
047fca5561
test_rtt: Another round of new features
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
d8520699b1
format: Allow printing test meta data to result file
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
8978374d92
csv, tsv: Fix printing of optional fields
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
bc14304f5e
test_rtt: Fix wrong option identifier
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
a366b80109
Fix formatting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
09bbd506cd
format-all: Exclude third-party or generated code
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
cad2da3a59
iec61850_sv: Fix IEC 61850-9-2 Sampled Values node and unit test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
4b896a8d7c
super_node: Fix configuration of idle_stop setting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
84f0ea9cb5
test_rtt: Fix test case numbering
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
bc95217766
test_rtt: Stop test cases properly in order to close file handles
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
1748f433fe
webrtc: Fix libdatachannel version detection
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
Steffen Vogel
e26a5c1b48
hypersim: Update UCM code for multiple signal values
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-05-02 10:30:12 +02:00
Niklas Eiling
ed05671a51
fpga: improve comments in register.cpp
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
c151be5cca
fpga: fix includes and various comments
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
f1776f8be4
fpga: improve comments for fastRead and fastWrite
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
a2ff0aca43
fix formatting in fpga
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
9cf926d84e
fpga: add lowLatencyMode setting
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This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
f498518236
fpga: update ips json in fpga.conf
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
2cc8cad115
fpga: expose methods for finer control over DMA data path
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d
fpga: improve dma latency
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
483293aec8
fpga: turn off all interrupts when using polling
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this improves the latency by at least 4 us in my setup.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
57d7396c09
fpga: optimize sg descriptor rings
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we are now using only one memory block for both sg rings. This is
required so that the SG interface can benefit from a read cache
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
9d1c45440c
Update .gitlab-ci.yml
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-15 07:52:03 +02:00
2529c7b2d7
Remove superfluous includes
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 18:56:28 +02:00
1204b47d29
test_rtt: Fix integration test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
718f6ca7eb
test_rtt: Fix cppcheck warnings
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
7fb7294ff0
Fix signal and format handling
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
7f8f7023b4
test_rtt: Port to C++
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
aad7fb478e
Fix code formatting in commented code section
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
0d231c28b8
Remove obsolete villas-test-rtt CLI application
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
0b04f4fd39
test_rtt: Show test process
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
c1f8d0fa80
stats: Indent histogram output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
3023ddaa3a
Fix some typos and harmonize log output
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 14:31:58 +02:00
abed592b9d
Harmonize formatting and style of example configuration files
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:38:57 +02:00
