108 commits

Author	SHA1	Message	Date
daniel-k	a5b5e317d4	wip implementing dependency parsing and proper memeory handling ... works and compiles so for. next is to implement different IP interfaces (Model, Interface, DataMover, Infrastructure, ...)	2018-01-10 11:02:08 +01:00
daniel-k	e590d1a350	add namespace villas::fpga and villas::fpga::ip and some renaming	2018-01-10 11:02:08 +01:00
daniel-k	b0e55e6fb2	current wip implementing card, many changes in ip too	2018-01-10 11:02:08 +01:00
daniel-k	d63c2b30bf	tests: compile main as C++	2018-01-10 11:02:08 +01:00
daniel-k	737a5851df	lib/card: start FPGA card prior to parsing ... Initializing IPs may want to probe the actual hardware for feature detection (e.g. DMA), so the card has to be started in order to access any memory on the card.	2017-11-28 11:26:41 +01:00
daniel-k	d67a120902	tests/dma: fix chunk size for simple DMA (should have been 4k)	2017-11-22 19:47:04 +01:00
daniel-k	c67c8aac5b	tests: add fpga.json and correctly parse it for unit tests	2017-11-22 19:46:07 +01:00
Steffen Vogel	c3164e93ef	imported source code from VILLASfpga repo and made it compile	2017-11-21 21:31:08 +01:00