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5502d3577b
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remove unused submodules
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2020-08-17 17:21:18 +02:00 |
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e5545aa17e
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emc: add initial code to flash FPGA bitstream via PCIe
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2020-07-08 17:16:43 +02:00 |
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eabae63714
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update submodules
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2020-07-08 15:24:01 +02:00 |
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c4fe7e4b07
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update libxil submodule
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2020-06-15 22:49:43 +02:00 |
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de566d441d
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move common code to VILLAScommon submodule
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2018-08-21 01:14:18 +02:00 |
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Daniel Krebs
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ff20f624a6
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thirdparty: add CLI11 and rang header-only libraries
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2018-06-04 14:20:06 +02:00 |
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Daniel Krebs
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1b2e7d312e
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common/memory: add host DMA memory allocator using udmabuf
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2018-05-15 18:04:24 +02:00 |
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Daniel Krebs
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10745f00b5
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libxil: update submodule
Only add temporary files to gitignore
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2018-02-13 16:15:28 +01:00 |
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Daniel Krebs
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aa33a8e028
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libxil: update upstream path
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2018-01-30 15:10:25 +01:00 |
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daniel-k
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28a7f2a3ee
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spdlog: fix handling of too long logger names
`whitespace` overflows because the result implicitly is an unsigned
value.
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2018-01-23 10:09:06 +01:00 |
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daniel-k
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f2a5e7af22
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spdlog: patch name formatter to implement fixed width names in format
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2018-01-10 15:42:03 +01:00 |
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daniel-k
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b33b4d27d9
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Merge commit '2cfd26b6ee2696a0e23b9caa72b89078d8428b94' as 'thirdparty/spdlog'
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2018-01-10 15:24:09 +01:00 |
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a288295e43
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created new repo for VILLASfpga
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2017-11-21 21:28:21 +01:00 |
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