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https://git.rwth-aachen.de/acs/public/villas/node/
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33 lines
662 B
Text
33 lines
662 B
Text
# SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
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# SPDX-License-Identifier: Apache-2.0
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logging = {
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level = "debug"
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}
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fpgas = {
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vc707 = {
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interface = "pcie",
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id = "10ee:7021",
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slot = "0000:88:00.0",
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do_reset = true,
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ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino-v2.json",
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polling = false,
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}
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}
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nodes = {
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fpga_0 = {
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type = "fpga",
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card = "vc707"
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connect = ["0->3", "3->dma", "0<-dma"]
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}
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}
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paths = (
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{
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in = "fpga_0"
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out = "fpga_0"
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hooks = ({ type = "print"})
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}
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)
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