mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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120 lines
3.6 KiB
C++
120 lines
3.6 KiB
C++
/* RTDS AXI-Stream RTT unit test.
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*
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* Author: Steffen Vogel <post@steffenvogel.de>
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* Author: Daniel Krebs <github@daniel-krebs.net>
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* SPDX-FileCopyrightText: 2018 Steffen Vogel <post@steffenvogel.de>
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* SPDX-FileCopyrightText: 2018 Daniel Krebs <github@daniel-krebs.net>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <list>
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#include <criterion/criterion.h>
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#include <villas/log.hpp>
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#include <villas/memory.hpp>
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#include <villas/utils.hpp>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include <villas/fpga/ips/rtds.hpp>
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#include <villas/fpga/ips/switch.hpp>
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#include <chrono>
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#include <villas/utils.hpp>
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#include "global.hpp"
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using namespace villas::fpga::ip;
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// cppcheck-suppress unknownMacro
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Test(fpga, rtds, .description = "RTDS") {
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auto logger = villas::logging.get("unit-test:rtds");
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std::list<villas::fpga::ip::RtdsGtfpga *> rtdsIps;
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std::list<villas::fpga::ip::Dma *> dmaIps;
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for (auto &ip : state.cards.front()->ips) {
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if (*ip ==
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villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")) {
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auto rtds = reinterpret_cast<villas::fpga::ip::RtdsGtfpga *>(ip.get());
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rtdsIps.push_back(rtds);
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}
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if (*ip == villas::fpga::Vlnv("xilinx.com:ip:axi_dma:")) {
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auto dma = reinterpret_cast<villas::fpga::ip::Dma *>(ip.get());
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dmaIps.push_back(dma);
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}
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}
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cr_assert(rtdsIps.size() > 0, "No RTDS IPs available to test");
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cr_assert(dmaIps.size() > 0, "No DMA IPs available to test RTDS with");
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for (auto rtds : rtdsIps) {
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for (auto dma : dmaIps) {
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logger->info("Testing {} with DMA {}", *rtds, *dma);
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rtds->dump();
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auto rtdsMaster = rtds->getMasterPort(rtds->masterPort);
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auto rtdsSlave = rtds->getSlavePort(rtds->slavePort);
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auto dmaMaster = dma->getMasterPort(dma->mm2sPort);
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auto dmaSlave = dma->getSlavePort(dma->s2mmPort);
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// rtds->connect(*rtds);
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// logger->info("loopback");
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// while (1);
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// rtds->connect(rtdsMaster, dmaSlave);
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// dma->connect(dmaMaster, rtdsSlave);
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auto mem = villas::HostRam::getAllocator().allocate<int32_t>(
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0x100 / sizeof(int32_t));
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// auto start = std::chrono::high_resolution_clock::now();
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for (int i = 1; i < 5; i++) {
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logger->info("RTT iteration {}", i);
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// logger->info("Prepare read");
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cr_assert(
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dma->read(mem.getMemoryBlock(), mem.getMemoryBlock().getSize()),
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"Failed to initiate DMA read");
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// logger->info("Wait read");
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const size_t bytesRead = dma->readComplete().bytes;
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cr_assert(bytesRead > 0, "Failed to complete DMA read");
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// logger->info("Bytes received: {}", bytesRead);
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// logger->info("Prepare write");
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cr_assert(dma->write(mem.getMemoryBlock(), bytesRead),
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"Failed to initiate DMA write");
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// logger->info("Wait write");
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// const size_t bytesWritten = dma->writeComplete();
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// cr_assert(bytesWritten > 0,
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// "Failed to complete DMA write");
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// usleep(5);
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// sched_yield();
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// for (int i = 0;)
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// rdtsc_sleep();
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// static constexpr int loopCount = 10000;
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// if (i % loopCount == 0) {
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// const auto end = std::chrono::high_resolution_clock::now();
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// auto durationUs = std::chrono::duration_cast<std::chrono::microseconds>(end - start) / loopCount;
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// logger->info("Avg. loop duration: {} us", durationUs.count());
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// start = std::chrono::high_resolution_clock::now();
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// }
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}
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logger->info(CLR_GRN("Passed"));
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}
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}
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}
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