mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
303 lines
7.4 KiB
C
303 lines
7.4 KiB
C
/** FPGA card.
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Institute for Automation of Complex Power Systems, EONERC
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* @license GNU General Public License (version 3)
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*
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* VILLASnode
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <unistd.h>
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#include "config.h"
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#include "log.h"
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#include "log_config.h"
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#include "list.h"
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#include "utils.h"
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#include "kernel/pci.h"
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#include "kernel/vfio.h"
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#include "fpga/ip.h"
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#include "fpga/card.h"
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int fpga_card_init(struct fpga_card *c, struct pci *pci, struct vfio_container *vc)
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{
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assert(c->state = STATE_DESTROYED);
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c->vfio_container = vc;
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c->pci = pci;
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list_init(&c->ips);
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/* Default values */
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c->filter.id.vendor = FPGA_PCI_VID_XILINX;
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c->filter.id.device = FPGA_PCI_PID_VFPGA;
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c->affinity = 0;
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c->do_reset = 0;
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c->state = STATE_INITIALIZED;
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return 0;
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}
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int fpga_card_parse(struct fpga_card *c, config_setting_t *cfg)
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{
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int ret;
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const char *slot, *id, *err;
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config_setting_t *cfg_ips, *cfg_slot, *cfg_id;
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c->name = config_setting_name(cfg);
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config_setting_lookup_int(cfg, "affinity", &c->affinity);
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config_setting_lookup_bool(cfg, "do_reset", &c->do_reset);
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cfg_slot = config_setting_get_member(cfg, "slot");
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if (cfg_slot) {
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slot = config_setting_get_string(cfg_slot);
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if (slot) {
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ret = pci_device_parse_slot(&c->filter, slot, &err);
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if (ret)
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cerror(cfg_slot, "Failed to parse PCI slot: %s", err);
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}
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else
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cerror(cfg_slot, "PCI slot must be a string");
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}
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cfg_id = config_setting_get_member(cfg, "id");
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if (cfg_id) {
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id = config_setting_get_string(cfg_id);
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if (id) {
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ret = pci_device_parse_id(&c->filter, (char*) id, &err);
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if (ret)
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cerror(cfg_id, "Failed to parse PCI id: %s", err);
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}
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else
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cerror(cfg_slot, "PCI ID must be a string");
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}
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cfg_ips = config_setting_get_member(cfg, "ips");
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if (!cfg_ips)
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cerror(cfg, "FPGA configuration is missing ips section");
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for (int i = 0; i < config_setting_length(cfg_ips); i++) {
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config_setting_t *cfg_ip = config_setting_get_elem(cfg_ips, i);
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const char *vlnv;
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struct fpga_ip_type *vt;
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struct fpga_ip ip = {
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.card = c,
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.state = STATE_DESTROYED
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};
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if (!config_setting_lookup_string(cfg, "vlnv", &vlnv))
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cerror(cfg, "FPGA IP core %s is missing the VLNV identifier", c->name);
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vt = fpga_ip_type_lookup(vlnv);
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if (!vt)
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cerror(cfg, "FPGA IP core VLNV identifier '%s' is invalid", vlnv);
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ret = fpga_ip_init(&ip, vt);
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if (ret)
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error("Failed to initalize FPGA IP core");
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ret = fpga_ip_parse(&ip, cfg_ip);
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if (ret)
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cerror(cfg_ip, "Failed to parse FPGA IP core");
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list_push(&c->ips, memdup(&ip, sizeof(ip)));
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}
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c->cfg = cfg;
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c->state = STATE_PARSED;
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return 0;
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}
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int fpga_card_parse_list(struct list *cards, config_setting_t *cfg)
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{
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int ret;
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if (!config_setting_is_group(cfg))
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cerror(cfg, "FPGA configuration section must be a group");
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for (int i = 0; i < config_setting_length(cfg); i++) {
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config_setting_t *cfg_fpga = config_setting_get_elem(cfg, i);
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struct fpga_card c;
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ret = fpga_card_parse(&c, cfg_fpga);
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if (ret)
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cerror(cfg_fpga, "Failed to parse FPGA card configuration");
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list_push(cards, memdup(&c, sizeof(c)));
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}
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return 0;
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}
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int fpga_card_start(struct fpga_card *c)
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{
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int ret;
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struct pci_device *pdev;
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assert(c->state == STATE_CHECKED);
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/* Search for FPGA card */
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pdev = pci_lookup_device(c->pci, &c->filter);
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if (!pdev)
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error("Failed to find PCI device");
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/* Attach PCIe card to VFIO container */
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ret = vfio_pci_attach(&c->vfio_device, c->vfio_container, pdev);
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if (ret)
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error("Failed to attach VFIO device");
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/* Map PCIe BAR */
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c->map = vfio_map_region(&c->vfio_device, VFIO_PCI_BAR0_REGION_INDEX);
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if (c->map == MAP_FAILED)
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serror("Failed to mmap() BAR0");
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/* Enable memory access and PCI bus mastering for DMA */
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ret = vfio_pci_enable(&c->vfio_device);
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if (ret)
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serror("Failed to enable PCI device");
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/* Reset system? */
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if (c->do_reset) {
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/* Reset / detect PCI device */
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ret = vfio_pci_reset(&c->vfio_device);
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if (ret)
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serror("Failed to reset PCI device");
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ret = fpga_card_reset(c);
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if (ret)
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error("Failed to reset FGPA card");
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}
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/* Initialize IP cores */
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for (size_t j = 0; j < list_length(&c->ips); j++) {
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struct fpga_ip *i = list_at(&c->ips, j);
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ret = fpga_ip_start(i);
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if (ret)
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error("Failed to initalize FPGA IP core: %s (%u)", i->name, ret);
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}
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c->state = STATE_STARTED;
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return 0;
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}
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int fpga_card_stop(struct fpga_card *c)
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{
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int ret;
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assert(c->state == STATE_STOPPED);
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for (size_t j = 0; j < list_length(&c->ips); j++) {
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struct fpga_ip *i = list_at(&c->ips, j);
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ret = fpga_ip_stop(i);
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if (ret)
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error("Failed to stop FPGA IP core: %s (%u)", i->name, ret);
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}
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c->state = STATE_STOPPED;
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return 0;
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}
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void fpga_card_dump(struct fpga_card *c)
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{
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info("VILLASfpga card:");
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{ INDENT
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info("Slot: %04x:%02x:%02x.%d", c->vfio_device.pci_device->slot.domain, c->vfio_device.pci_device->slot.bus, c->vfio_device.pci_device->slot.device, c->vfio_device.pci_device->slot.function);
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info("Vendor ID: %04x", c->vfio_device.pci_device->id.vendor);
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info("Device ID: %04x", c->vfio_device.pci_device->id.device);
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info("Class ID: %04x", c->vfio_device.pci_device->id.class);
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info("BAR0 mapped at %p", c->map);
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info("IP blocks:");
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for (size_t j = 0; j < list_length(&c->ips); j++) { INDENT
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struct fpga_ip *i = list_at(&c->ips, j);
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fpga_ip_dump(i);
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}
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}
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vfio_dump(c->vfio_device.group->container);
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}
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int fpga_card_check(struct fpga_card *c)
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{
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/* Check FPGA configuration */
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c->reset = fpga_vlnv_lookup(&c->ips, &(struct fpga_vlnv) { "xilinx.com", "ip", "axi_gpio", NULL });
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if (!c->reset)
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error("FPGA is missing a reset controller");
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c->intc = fpga_vlnv_lookup(&c->ips, &(struct fpga_vlnv) { "acs.eonerc.rwth-aachen.de", "user", "axi_pcie_intc", NULL });
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if (!c->intc)
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error("FPGA is missing a interrupt controller");
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c->sw = fpga_vlnv_lookup(&c->ips, &(struct fpga_vlnv) { "xilinx.com", "ip", "axis_interconnect", NULL });
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if (!c->sw)
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warn("FPGA is missing an AXI4-Stream switch");
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return 0;
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}
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int fpga_card_destroy(struct fpga_card *c)
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{
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list_destroy(&c->ips, (dtor_cb_t) fpga_ip_destroy, true);
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return 0;
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}
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int fpga_card_reset(struct fpga_card *c)
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{
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int ret;
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char state[4096];
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/* Save current state of PCI configuration space */
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ret = pread(c->vfio_device.fd, state, sizeof(state), (off_t) VFIO_PCI_CONFIG_REGION_INDEX << 40);
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if (ret != sizeof(state))
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return -1;
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uint32_t *rst_reg = (uint32_t *) (c->map + c->reset->baseaddr);
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debug(3, "FPGA: reset");
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rst_reg[0] = 1;
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usleep(100000);
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/* Restore previous state of PCI configuration space */
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ret = pwrite(c->vfio_device.fd, state, sizeof(state), (off_t) VFIO_PCI_CONFIG_REGION_INDEX << 40);
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if (ret != sizeof(state))
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return -1;
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/* After reset the value should be zero again */
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if (rst_reg[0])
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return -2;
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c->state = STATE_INITIALIZED;
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return 0;
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}
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