mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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132 lines
No EOL
2.7 KiB
C
132 lines
No EOL
2.7 KiB
C
/** FIFO related helper functions
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*
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* These functions present a simpler interface to Xilinx' FIFO driver (XLlFifo_*)
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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**********************************************************************************/
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#include <unistd.h>
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#include "utils.h"
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#include "plugin.h"
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#include "fpga/ip.h"
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#include "fpga/card.h"
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#include "fpga/ips/fifo.h"
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#include "fpga/ips/intc.h"
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int fifo_start(struct fpga_ip *c)
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{
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int ret;
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struct fpga_card *f = c->card;
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struct fifo *fifo = c->_vd;
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XLlFifo *xfifo = &fifo->inst;
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XLlFifo_Config fifo_cfg = {
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.BaseAddress = (uintptr_t) f->map + c->baseaddr,
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.Axi4BaseAddress = (uintptr_t) c->card->map + fifo->baseaddr_axi4,
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.Datainterface = (fifo->baseaddr_axi4 != -1) ? 1 : 0 /* use AXI4 for Data, AXI4-Lite for control */
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};
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ret = XLlFifo_CfgInitialize(xfifo, &fifo_cfg, (uintptr_t) c->card->map + c->baseaddr);
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if (ret != XST_SUCCESS)
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return -1;
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XLlFifo_IntEnable(xfifo, XLLF_INT_RC_MASK); /* Receive complete IRQ */
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return 0;
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}
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int fifo_stop(struct fpga_ip *c)
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{
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struct fifo *fifo = c->_vd;
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XLlFifo *xfifo = &fifo->inst;
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XLlFifo_IntDisable(xfifo, XLLF_INT_RC_MASK); /* Receive complete IRQ */
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return 0;
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}
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ssize_t fifo_write(struct fpga_ip *c, char *buf, size_t len)
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{
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struct fifo *fifo = c->_vd;
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XLlFifo *xllfifo = &fifo->inst;
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uint32_t tdfv;
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tdfv = XLlFifo_TxVacancy(xllfifo);
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if (tdfv < len)
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return -1;
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XLlFifo_Write(xllfifo, buf, len);
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XLlFifo_TxSetLen(xllfifo, len);
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return len;
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}
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ssize_t fifo_read(struct fpga_ip *c, char *buf, size_t len)
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{
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struct fifo *fifo = c->_vd;
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XLlFifo *xllfifo = &fifo->inst;
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size_t nextlen = 0;
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uint32_t rxlen;
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while (!XLlFifo_IsRxDone(xllfifo))
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intc_wait(c->card->intc, c->irq);
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XLlFifo_IntClear(xllfifo, XLLF_INT_RC_MASK);
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/* Get length of next frame */
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rxlen = XLlFifo_RxGetLen(xllfifo);
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nextlen = MIN(rxlen, len);
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/* Read from FIFO */
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XLlFifo_Read(xllfifo, buf, nextlen);
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return nextlen;
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}
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int fifo_parse(struct fpga_ip *c)
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{
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struct fifo *fifo = c->_vd;
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int baseaddr_axi4;
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if (config_setting_lookup_int(c->cfg, "baseaddr_axi4", &baseaddr_axi4))
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fifo->baseaddr_axi4 = baseaddr_axi4;
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else
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fifo->baseaddr_axi4 = -1;
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return 0;
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}
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int fifo_reset(struct fpga_ip *c)
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{
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struct fifo *fifo = c->_vd;
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XLlFifo_Reset(&fifo->inst);
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return 0;
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}
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static struct plugin p = {
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.name = "Xilinx's AXI4 FIFO data mover",
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.description = "",
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.type = PLUGIN_TYPE_FPGA_IP,
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.ip = {
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.vlnv = { "xilinx.com", "ip", "axi_fifo_mm_s", NULL },
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.type = FPGA_IP_TYPE_DM_FIFO,
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.start = fifo_start,
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.stop = fifo_stop,
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.parse = fifo_parse,
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.reset = fifo_reset,
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.size = sizeof(struct fifo)
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}
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};
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REGISTER_PLUGIN(&p) |