mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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64 lines
No EOL
2.1 KiB
C
64 lines
No EOL
2.1 KiB
C
/** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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**********************************************************************************/
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#include <stdint.h>
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#include "log.h"
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#include "utils.h"
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#include "plugin.h"
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#include "fpga/ip.h"
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#include "fpga/card.h"
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#include "fpga/ips/rtds_axis.h"
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void rtds_axis_dump(struct fpga_ip *c)
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{
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/* Check RTDS_Axis registers */
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uint32_t *regs = (uint32_t *) (c->card->map + c->baseaddr);
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uint32_t sr = regs[RTDS_AXIS_SR_OFFSET/4];
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info("RTDS AXI Stream interface details");
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{ INDENT
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info("RTDS status: %#08x", sr);
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{ INDENT
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info("Card detected: %s", sr & RTDS_AXIS_SR_CARDDETECTED ? GRN("yes") : RED("no"));
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info("Link up: %s", sr & RTDS_AXIS_SR_LINKUP ? GRN("yes") : RED("no"));
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info("TX queue full: %s", sr & RTDS_AXIS_SR_TX_FULL ? RED("yes") : GRN("no"));
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info("TX in progress: %s", sr & RTDS_AXIS_SR_TX_INPROGRESS ? YEL("yes") : "no");
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info("Case running: %s", sr & RTDS_AXIS_SR_CASE_RUNNING ? GRN("yes") : RED("no"));
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}
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info("RTDS control: %#08x", regs[RTDS_AXIS_CR_OFFSET/4]);
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info("RTDS IRQ coalesc: %u", regs[RTDS_AXIS_COALESC_OFFSET/4]);
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info("RTDS IRQ version: %#06x", regs[RTDS_AXIS_VERSION_OFFSET/4]);
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info("RTDS IRQ multi-rate: %u", regs[RTDS_AXIS_MRATE/4]);
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info("RTDS timestep counter: %lu", (uint64_t) regs[RTDS_AXIS_TSCNT_LOW_OFFSET/4] | (uint64_t) regs[RTDS_AXIS_TSCNT_HIGH_OFFSET/4] << 32);
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info("RTDS timestep period: %.3f uS", rtds_axis_dt(c) * 1e6);
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}
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}
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double rtds_axis_dt(struct fpga_ip *c)
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{
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uint32_t *regs = (uint32_t *) (c->card->map + c->baseaddr);
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uint16_t dt = regs[RTDS_AXIS_TS_PERIOD_OFFSET/4];
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return (dt == 0xFFFF) ? -1.0 : (double) dt / RTDS_HZ;
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}
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static struct plugin p = {
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.name = "RTDS's AXI4-Stream - GTFPGA interface",
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.description = "",
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.type = PLUGIN_TYPE_FPGA_IP,
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.ip = {
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.vlnv = { "acs.eonerc.rwth-aachen.de", "user", "rtds_axis", NULL },
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.type = FPGA_IP_TYPE_INTERFACE,
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.dump = rtds_axis_dump,
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.size = 0
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}
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};
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REGISTER_PLUGIN(&p) |