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https://git.rwth-aachen.de/acs/public/villas/node/
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99 lines
4.7 KiB
C++
99 lines
4.7 KiB
C++
/* Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
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*
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* Author: Steffen Vogel <post@steffenvogel.de>
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* SPDX-FileCopyrightText: 2017 Steffen Vogel <post@steffenvogel.de>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <cstdint>
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#include <villas/utils.hpp>
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#include <villas/fpga/ips/rtds.hpp>
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#define RTDS_HZ 100000000 // 100 MHz
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#define RTDS_AXIS_MAX_TX \
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64 // The amount of values which is supported by the VIILASfpga card
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#define RTDS_AXIS_MAX_RX \
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64 // The amount of values which is supported by the VIILASfpga card
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// Register offsets
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#define RTDS_AXIS_SR_OFFSET \
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0x00 // Status Register (read-only). See RTDS_AXIS_SR_* constant.
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#define RTDS_AXIS_CR_OFFSET 0x04 // Control Register (read/write)
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#define RTDS_AXIS_TSCNT_LOW_OFFSET \
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0x08 // Lower 32 bits of timestep counter (read-only).
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#define RTDS_AXIS_TSCNT_HIGH_OFFSET \
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0x0C // Higher 32 bits of timestep counter (read-only).
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#define RTDS_AXIS_TS_PERIOD_OFFSET \
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0x10 // Period in clock cycles of previous timestep (read-only).
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#define RTDS_AXIS_COALESC_OFFSET 0x14 // IRQ Coalescing register (read/write).
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#define RTDS_AXIS_VERSION_OFFSET \
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0x18 // 16 bit version field passed back to the rack for version reporting (visible from “status” command, read/write).
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#define RTDS_AXIS_MRATE 0x1C // Multi-rate register
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// Status register bits
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#define RTDS_AXIS_SR_CARDDETECTED \
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(1 << 0) // ‘1’ when RTDS software has detected and configured card.
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#define RTDS_AXIS_SR_LINKUP \
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(1 << 1) // ‘1’ when RTDS communication link has been negotiated.
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#define RTDS_AXIS_SR_TX_FULL \
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(1 \
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<< 2) // Tx buffer is full, writes that happen when UserTxFull=’1’ will be dropped (Throttling / buffering is performed by hardware).
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#define RTDS_AXIS_SR_TX_INPROGRESS \
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(1 << 3) // Indicates when data is being put on link.
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#define RTDS_AXIS_SR_CASE_RUNNING \
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(1 << 4) // There is currently a simulation running.
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// Control register bits
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#define RTDS_AXIS_CR_DISABLE_LINK 0 // Disable SFP TX when set
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using namespace villas::fpga::ip;
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void RtdsGtfpga::dump() {
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// Check RTDS_Axis registers
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const uint32_t sr = readMemory<uint32_t>(registerMemory, RTDS_AXIS_SR_OFFSET);
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logger->info("RTDS AXI Stream interface details:");
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logger->info("RTDS status: {:#x}", sr);
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logger->info(" Card detected: {}",
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sr & RTDS_AXIS_SR_CARDDETECTED ? CLR_GRN("yes") : CLR_RED("no"));
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logger->info(" Link up: {}",
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sr & RTDS_AXIS_SR_LINKUP ? CLR_GRN("yes") : CLR_RED("no"));
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logger->info(" TX queue full: {}",
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sr & RTDS_AXIS_SR_TX_FULL ? CLR_RED("yes") : CLR_GRN("no"));
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logger->info(" TX in progress: {}",
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sr & RTDS_AXIS_SR_TX_INPROGRESS ? CLR_YEL("yes") : "no");
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logger->info(" Case running: {}",
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sr & RTDS_AXIS_SR_CASE_RUNNING ? CLR_GRN("yes") : CLR_RED("no"));
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logger->info("RTDS control: {:#x}",
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readMemory<uint32_t>(registerMemory, RTDS_AXIS_CR_OFFSET));
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logger->info("RTDS IRQ coalesc: {}",
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readMemory<uint32_t>(registerMemory, RTDS_AXIS_COALESC_OFFSET));
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logger->info("RTDS IRQ version: {:#x}",
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readMemory<uint32_t>(registerMemory, RTDS_AXIS_VERSION_OFFSET));
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logger->info("RTDS IRQ multi-rate: {}",
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readMemory<uint32_t>(registerMemory, RTDS_AXIS_MRATE));
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const uint64_t timestepLow =
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readMemory<uint32_t>(registerMemory, RTDS_AXIS_TSCNT_LOW_OFFSET);
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const uint64_t timestepHigh =
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readMemory<uint32_t>(registerMemory, RTDS_AXIS_TSCNT_HIGH_OFFSET);
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const uint64_t timestep = (timestepHigh << 32) | timestepLow;
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logger->info("RTDS timestep counter: {}", timestep);
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logger->info("RTDS timestep period: {:.3f} us", getDt() * 1e6);
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}
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double RtdsGtfpga::getDt() {
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const auto dt =
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readMemory<uint16_t>(registerMemory, RTDS_AXIS_TS_PERIOD_OFFSET);
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return (dt == 0xFFFF) ? 0.0 : (double)dt / RTDS_HZ;
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}
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static char n[] = "rtds_gtfpga";
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static char d[] = "RTDS's AXI4-Stream - GTFPGA interface";
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static char v[] = "acs.eonerc.rwth-aachen.de:user:rtds_axis:";
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static NodePlugin<RtdsGtfpga, n, d, v> f;
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