mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
334 lines
11 KiB
C++
334 lines
11 KiB
C++
/* FIFO unit test.
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*
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* Author: Daniel Krebs <github@daniel-krebs.net>
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* SPDX-FileCopyrightText: 2017 Daniel Krebs <github@daniel-krebs.net>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <criterion/criterion.h>
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#include <iostream>
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#include <villas/fpga/card.hpp>
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#include <villas/log.hpp>
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#include <villas/memory.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include <villas/fpga/ips/gpu2rtds.hpp>
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#include <villas/fpga/ips/rtds.hpp>
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#include <villas/fpga/ips/rtds2gpu.hpp>
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#include <villas/fpga/ips/switch.hpp>
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#include <villas/gpu.hpp>
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#include "global.hpp"
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using namespace villas;
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static constexpr size_t SAMPLE_SIZE = 4;
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static constexpr size_t SAMPLE_COUNT = 1;
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static constexpr size_t FRAME_SIZE = SAMPLE_COUNT * SAMPLE_SIZE;
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static constexpr size_t DOORBELL_OFFSET = SAMPLE_COUNT;
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static constexpr size_t DATA_OFFSET = 0;
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static void dumpMem(const uint32_t *addr, size_t len) {
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const size_t bytesPerLine = 16;
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const size_t lines = (len) / bytesPerLine + 1;
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const uint8_t *buf = reinterpret_cast<const uint8_t *>(addr);
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size_t bytesRead = 0;
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for (size_t line = 0; line < lines; line++) {
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const unsigned base = line * bytesPerLine;
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printf("0x%04x: ", base);
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for (size_t i = 0; i < bytesPerLine && bytesRead < len; i++) {
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printf("0x%02x ", buf[base + i]);
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bytesRead++;
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}
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puts("");
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}
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}
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// cppcheck-suppress unknownMacro
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Test(fpga, rtds2gpu_loopback_dma, .description = "Rtds2Gpu") {
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auto logger = logging.get("unit-test:rtds2gpu");
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for (auto &ip : state.cards.front()->ips) {
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if (*ip != fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:rtds2gpu:"))
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continue;
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logger->info("Testing {}", *ip);
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// Collect neccessary IPs
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auto rtds2gpu = std::dynamic_pointer_cast<fpga::ip::Rtds2Gpu>(ip);
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auto axiSwitch = std::dynamic_pointer_cast<fpga::ip::AxiStreamSwitch>(
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state.cards.front()->lookupIp(
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fpga::Vlnv("xilinx.com:ip:axis_switch:")));
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auto dma = std::dynamic_pointer_cast<fpga::ip::Dma>(
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state.cards.front()->lookupIp(fpga::Vlnv("xilinx.com:ip:axi_dma:")));
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auto gpu2rtds = std::dynamic_pointer_cast<fpga::ip::Gpu2Rtds>(
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state.cards.front()->lookupIp(
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fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:gpu2rtds:")));
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auto rtds =
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std::dynamic_pointer_cast<fpga::ip::Rtds>(state.cards.front()->lookupIp(
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fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")));
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cr_assert_not_null(axiSwitch, "No AXI switch IP found");
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cr_assert_not_null(dma, "No DMA IP found");
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cr_assert_not_null(gpu2rtds, "No Gpu2Rtds IP found");
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cr_assert_not_null(rtds, "RTDS IP not found");
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rtds2gpu.dump(spdlog::level::debug);
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gpu2rtds->dump(spdlog::level::debug);
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// Allocate and prepare memory
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// Allocate space for all samples and doorbell register
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auto dmaMemSrc =
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HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
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auto dmaMemDst =
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HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
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auto dmaMemDst2 =
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HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
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memset(&dmaMemSrc, 0x11, dmaMemSrc.getMemoryBlock().getSize());
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memset(&dmaMemDst, 0x55, dmaMemDst.getMemoryBlock().getSize());
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memset(&dmaMemDst2, 0x77, dmaMemDst2.getMemoryBlock().getSize());
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const uint32_t *dataSrc = &dmaMemSrc[DATA_OFFSET];
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const uint32_t *dataDst = &dmaMemDst[DATA_OFFSET];
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const uint32_t *dataDst2 = &dmaMemDst2[0];
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dumpMem(dataSrc, dmaMemSrc.getMemoryBlock().getSize());
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dumpMem(dataDst, dmaMemDst.getMemoryBlock().getSize());
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dumpMem(dataDst2, dmaMemDst2.getMemoryBlock().getSize());
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// Connect AXI Stream from DMA to Rtds2Gpu IP
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cr_assert(dma->connect(rtds2gpu));
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cr_assert(rtds2gpu.startOnce(dmaMemDst.getMemoryBlock(), SAMPLE_COUNT,
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DATA_OFFSET * 4, DOORBELL_OFFSET * 4),
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"Preparing Rtds2Gpu IP failed");
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cr_assert(dma->write(dmaMemSrc.getMemoryBlock(), FRAME_SIZE),
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"Starting DMA MM2S transfer failed");
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cr_assert(dma->writeComplete(), "DMA failed");
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while (not rtds2gpu.isFinished())
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;
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const uint32_t *doorbellDst = &dmaMemDst[DOORBELL_OFFSET];
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rtds2gpu.dump(spdlog::level::info);
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rtds2gpu.dumpDoorbell(*doorbellDst);
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cr_assert(memcmp(dataSrc, dataDst, FRAME_SIZE) == 0, "Memory not equal");
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for (size_t i = 0; i < SAMPLE_COUNT; i++)
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gpu2rtds->registerFrames[i] = dmaMemDst[i];
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// Connect AXI Stream from Gpu2Rtds IP to DMA
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cr_assert(gpu2rtds->connect(*dma));
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cr_assert(dma->read(dmaMemDst2.getMemoryBlock(), FRAME_SIZE),
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"Starting DMA S2MM transfer failed");
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cr_assert(gpu2rtds->startOnce(SAMPLE_COUNT),
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"Preparing Gpu2Rtds IP failed");
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cr_assert(dma->readComplete(), "DMA failed");
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while (not gpu2rtds->isFinished())
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;
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cr_assert(memcmp(dataSrc, dataDst2, FRAME_SIZE) == 0, "Memory not equal");
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dumpMem(dataSrc, dmaMemSrc.getMemoryBlock().getSize());
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dumpMem(dataDst, dmaMemDst.getMemoryBlock().getSize());
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dumpMem(dataDst2, dmaMemDst2.getMemoryBlock().getSize());
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logger->info(CLR_GRN("Passed"));
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}
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}
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// cppcheck-suppress unknownMacro
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Test(fpga, rtds2gpu_rtt_cpu, .description = "Rtds2Gpu RTT via CPU") {
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auto logger = logging.get("unit-test:rtds2gpu");
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// Collect neccessary IPs
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auto gpu2rtds = std::dynamic_pointer_cast<fpga::ip::Gpu2Rtds>(
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state.cards.front()->lookupIp(
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fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:gpu2rtds:")));
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auto rtds2gpu = std::dynamic_pointer_cast<fpga::ip::Rtds2Gpu>(
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state.cards.front()->lookupIp(
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fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:rtds2gpu:")));
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cr_assert_not_null(gpu2rtds, "No Gpu2Rtds IP found");
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cr_assert_not_null(rtds2gpu, "No Rtds2Gpu IP not found");
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for (auto &ip : state.cards.front()->ips) {
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if (*ip != fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:"))
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continue;
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auto &rtds = dynamic_cast<fpga::ip::Rtds &>(*ip);
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logger->info("Testing {}", rtds);
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auto dmaRam =
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HostDmaRam::getAllocator().allocate<uint32_t>(SAMPLE_COUNT + 1);
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uint32_t *data = &dmaRam[DATA_OFFSET];
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uint32_t *doorbell = &dmaRam[DOORBELL_OFFSET];
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// TEST: rtds loopback via switch, this should always work and have RTT=1
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//cr_assert(rtds.connect(rtds));
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//logger->info("loopback");
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//while (1);
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cr_assert(rtds.connect(*rtds2gpu));
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cr_assert(gpu2rtds->connect(rtds));
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for (size_t i = 1; i <= 10000;) {
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rtds2gpu->doorbellReset(*doorbell);
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rtds2gpu->startOnce(dmaRam.getMemoryBlock(), SAMPLE_COUNT,
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DATA_OFFSET * 4, DOORBELL_OFFSET * 4);
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// Wait by polling rtds2gpu IP or ...
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// while (not rtds2gpu->isFinished());
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// Wait by polling (local) doorbell register (= just memory)
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while (not rtds2gpu->doorbellIsValid(*doorbell))
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;
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// Copy samples to gpu2rtds IP
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for (size_t i = 0; i < SAMPLE_COUNT; i++) {
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gpu2rtds->registerFrames[i] = data[i];
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}
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// Waiting for gpu2rtds is not strictly required
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gpu2rtds->startOnce(SAMPLE_COUNT);
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//while (not gpu2rtds->isFinished());
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if (i % 1000 == 0) {
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logger->info("Successful iterations {}, data {}", i, data[0]);
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rtds2gpu->dump();
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rtds2gpu->dumpDoorbell(data[1]);
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}
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}
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logger->info(CLR_GRN("Passed"));
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}
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}
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void gpu_rtds_rtt_start(volatile uint32_t *dataIn,
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volatile reg_doorbell_t *doorbellIn,
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volatile uint32_t *dataOut,
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volatile fpga::ip::ControlRegister *controlRegister);
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void gpu_rtds_rtt_stop();
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// cppcheck-suppress unknownMacro
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Test(fpga, rtds2gpu_rtt_gpu, .description = "Rtds2Gpu RTT via GPU") {
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auto logger = logging.get("unit-test:rtds2gpu");
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// Collect neccessary IPs
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auto gpu2rtds = std::dynamic_pointer_cast<fpga::ip::Gpu2Rtds>(
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state.cards.front()->lookupIp(
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fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:gpu2rtds:")));
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auto rtds2gpu = std::dynamic_pointer_cast<fpga::ip::Rtds2Gpu>(
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state.cards.front()->lookupIp(
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fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:rtds2gpu:")));
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cr_assert_not_null(gpu2rtds, "No Gpu2Rtds IP found");
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cr_assert_not_null(rtds2gpu, "No Rtds2Gpu IP not found");
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auto gpuPlugin = Registry::lookup<GpuFactory>("cuda");
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cr_assert_not_null(gpuPlugin, "No GPU plugin found");
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auto gpus = gpuPlugin->make();
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cr_assert(gpus.size() > 0, "No GPUs found");
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// Just get first cpu
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auto &gpu = gpus.front();
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// Allocate memory on GPU and make accessible by to PCIe/FPGA
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auto gpuRam = gpu->getAllocator().allocate<uint32_t>(SAMPLE_COUNT + 1);
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cr_assert(gpu->makeAccessibleToPCIeAndVA(gpuRam.getMemoryBlock()));
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// Make Gpu2Rtds IP register memory on FPGA accessible to GPU
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cr_assert(
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gpu->makeAccessibleFromPCIeOrHostRam(gpu2rtds->getRegisterMemory()));
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auto tr = gpu->translate(gpuRam.getMemoryBlock());
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auto dataIn = reinterpret_cast<uint32_t *>(
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tr.getLocalAddr(DATA_OFFSET * sizeof(uint32_t)));
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auto doorbellIn = reinterpret_cast<reg_doorbell_t *>(
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tr.getLocalAddr(DOORBELL_OFFSET * sizeof(uint32_t)));
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auto gpu2rtdsRegisters = gpu->translate(gpu2rtds->getRegisterMemory());
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auto frameRegister = reinterpret_cast<uint32_t *>(
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gpu2rtdsRegisters.getLocalAddr(gpu2rtds->registerFrameOffset));
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auto controlRegister = reinterpret_cast<fpga::ip::ControlRegister *>(
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gpu2rtdsRegisters.getLocalAddr(gpu2rtds->registerControlAddr));
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// auto doorbellInCpu = reinterpret_cast<reg_doorbell_t*>(&gpuRam[DOORBELL_OFFSET]);
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for (auto &ip : state.cards.front()->ips) {
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if (*ip != fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:"))
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continue;
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auto &rtds = dynamic_cast<fpga::ip::Rtds &>(*ip);
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logger->info("Testing {}", rtds);
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// TEST: rtds loopback via switch, this should always work and have RTT=1
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//cr_assert(rtds.connect(rtds));
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//logger->info("loopback");
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//while (1);
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cr_assert(rtds.connect(*rtds2gpu));
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cr_assert(gpu2rtds->connect(rtds));
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// Launch once so they are configured
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cr_assert(rtds2gpu->startOnce(gpuRam.getMemoryBlock(), SAMPLE_COUNT,
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DATA_OFFSET * 4, DOORBELL_OFFSET * 4));
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cr_assert(gpu2rtds->startOnce(SAMPLE_COUNT));
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rtds2gpu->setAutoRestart(true);
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rtds2gpu->start();
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logger->info("GPU RTT RTDS");
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std::string dummy;
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gpu_rtds_rtt_start(dataIn, doorbellIn, frameRegister, controlRegister);
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// while (1) {
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// cr_assert(rtds2gpu->startOnce(gpuRam.getMemoryBlock(), SAMPLE_COUNT, DATA_OFFSET * 4, DOORBELL_OFFSET * 4));
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// }
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// for (int i = 0; i < 10000; i++) {
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// while (not doorbellInCpu->is_valid);
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// logger->debug("received data");
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// }
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// logger->info("Press enter to cancel");
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// std::cin >> dummy;
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while (1) {
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sleep(1);
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// logger->debug("Current sequence number: {}", doorbellInCpu->seq_nr);
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logger->debug("Still running");
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}
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gpu_rtds_rtt_stop();
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logger->info(CLR_GRN("Passed"));
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}
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}
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