mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-30 00:00:11 +01:00
427 lines
12 KiB
JSON
427 lines
12 KiB
JSON
{
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"affinity": 1,
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"stats": 3,
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"name": "villas-acs",
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"logging": {
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"level": 5,
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"faciltities": [
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"path",
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"socket"
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],
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"file": "/var/log/villas-node.log",
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"syslog": true
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},
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"http": {
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"enabled": true,
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"htdocs": "/villas/web/socket/",
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"port": 80
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},
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"plugins": [
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"simple_circuit.so",
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"example_hook.so"
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],
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"fpgas": {
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"vc707": {
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"id": "10ee:7022",
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"slot": "03:00.0",
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"do_reset": true,
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"ips": {
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"bram_0_axi_bram_ctrl_0": {
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"vlnv": "xilinx.com:ip:axi_bram_ctrl:4.0",
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"size": 8192
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},
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"hier_0_axi_dma_axi_dma_0": {
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"vlnv": "xilinx.com:ip:axi_dma:7.1",
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"memory-view": {
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"M_AXI_SG": {
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"bram_0_axi_bram_ctrl_0": {
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"Mem0": {
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"baseaddr": 0,
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"highaddr": 8191,
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"size": 8192
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}
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},
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"hier_0_axi_dma_axi_dma_1": {
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"Reg": {
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"baseaddr": 8192,
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"highaddr": 12287,
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"size": 4096
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}
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},
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"hier_0_axi_dma_axi_dma_0": {
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"Reg": {
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"baseaddr": 12288,
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"highaddr": 16383,
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"size": 4096
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}
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},
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"timer_0_axi_timer_0": {
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"Reg": {
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"baseaddr": 16384,
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"highaddr": 20479,
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"size": 4096
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}
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},
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"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
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"Reg": {
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"baseaddr": 20480,
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"highaddr": 24575,
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"size": 4096
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}
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},
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"hier_0_axi_fifo_mm_s_0": {
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"Mem0": {
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"baseaddr": 24576,
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"highaddr": 28671,
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"size": 4096
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},
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"Mem1": {
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"baseaddr": 49152,
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"highaddr": 57343,
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"size": 8192
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}
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},
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"pcie_0_axi_reset_0": {
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"Reg": {
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"baseaddr": 28672,
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"highaddr": 32767,
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"size": 4096
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}
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},
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"hier_0_rtds_axis_0": {
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"reg0": {
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"baseaddr": 32768,
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"highaddr": 36863,
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"size": 4096
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}
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},
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"hier_0_hls_dft_0": {
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"Reg": {
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"baseaddr": 36864,
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"highaddr": 40959,
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"size": 4096
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}
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},
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"pcie_0_axi_pcie_intc_0": {
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"Reg": {
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"baseaddr": 45056,
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"highaddr": 49151,
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"size": 4096
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}
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},
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"pcie_0_axi_pcie_0": {
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"CTL0": {
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"baseaddr": 268435456,
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"highaddr": 536870911,
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"size": 268435456
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}
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}
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},
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"M_AXI_MM2S": {
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"pcie_0_axi_pcie_0": {
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"BAR0": {
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"baseaddr": 0,
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"highaddr": 4294967295,
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"size": 4294967296
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}
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}
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},
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"M_AXI_S2MM": {
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"pcie_0_axi_pcie_0": {
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"BAR0": {
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"baseaddr": 0,
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"highaddr": 4294967295,
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"size": 4294967296
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}
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}
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}
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},
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:1",
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"name": "MM2S"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:1",
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"name": "S2MM"
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}
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],
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"irqs": {
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"mm2s_introut": "pcie_0_axi_pcie_intc_0:3",
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"s2mm_introut": "pcie_0_axi_pcie_intc_0:4"
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}
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},
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"hier_0_axi_dma_axi_dma_1": {
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"vlnv": "xilinx.com:ip:axi_dma:7.1",
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"memory-view": {
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"M_AXI_MM2S": {
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"pcie_0_axi_pcie_0": {
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"BAR0": {
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"baseaddr": 0,
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"highaddr": 4294967295,
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"size": 4294967296
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}
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}
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},
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"M_AXI_S2MM": {
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"pcie_0_axi_pcie_0": {
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"BAR0": {
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"baseaddr": 0,
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"highaddr": 4294967295,
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"size": 4294967296
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}
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}
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}
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},
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:6",
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"name": "MM2S"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:6",
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"name": "S2MM"
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}
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],
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"irqs": {
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"mm2s_introut": "pcie_0_axi_pcie_intc_0:3",
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"s2mm_introut": "pcie_0_axi_pcie_intc_0:4"
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}
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},
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"hier_0_axi_fifo_mm_s_0": {
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"vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1",
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:2",
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"name": "STR_TXD"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:2",
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"name": "STR_RXD"
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}
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],
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"irqs": {
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"interrupt": "pcie_0_axi_pcie_intc_0:2"
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}
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},
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"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
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"vlnv": "xilinx.com:ip:axis_switch:1.1",
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:3",
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"name": "M03_AXIS"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:3",
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"name": "S03_AXIS"
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},
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:4",
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"name": "M04_AXIS"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:4",
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"name": "S04_AXIS"
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}
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],
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"num_ports": 7
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},
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"hier_0_hls_dft_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.1",
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:5",
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"name": "output_r"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:5",
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"name": "input_r"
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}
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],
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"irqs": {
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"interrupt": "pcie_0_axi_pcie_intc_0:1"
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}
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},
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"hier_0_rtds_axis_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0",
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"ports": [
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{
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"role": "master",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:0",
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"name": "m_axis"
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},
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{
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"role": "slave",
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"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:0",
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"name": "s_axis"
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}
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],
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"irqs": {
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"irq_ts": "pcie_0_axi_pcie_intc_0:5",
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"irq_overflow": "pcie_0_axi_pcie_intc_0:6",
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"irq_case": "pcie_0_axi_pcie_intc_0:7"
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}
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},
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"pcie_0_axi_pcie_0": {
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"vlnv": "xilinx.com:ip:axi_pcie:2.8",
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"memory-view": {
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"M_AXI": {
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"bram_0_axi_bram_ctrl_0": {
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"Mem0": {
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"baseaddr": 0,
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"highaddr": 8191,
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"size": 8192
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}
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},
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"hier_0_axi_dma_axi_dma_1": {
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"Reg": {
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"baseaddr": 8192,
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"highaddr": 12287,
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"size": 4096
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}
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},
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"hier_0_axi_dma_axi_dma_0": {
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"Reg": {
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"baseaddr": 12288,
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"highaddr": 16383,
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"size": 4096
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}
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},
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"timer_0_axi_timer_0": {
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"Reg": {
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"baseaddr": 16384,
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"highaddr": 20479,
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"size": 4096
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}
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},
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"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
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"Reg": {
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"baseaddr": 20480,
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"highaddr": 24575,
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"size": 4096
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}
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},
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"hier_0_axi_fifo_mm_s_0": {
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"Mem0": {
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"baseaddr": 24576,
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"highaddr": 28671,
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"size": 4096
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},
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"Mem1": {
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"baseaddr": 49152,
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"highaddr": 57343,
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"size": 8192
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}
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},
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"pcie_0_axi_reset_0": {
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"Reg": {
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"baseaddr": 28672,
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"highaddr": 32767,
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"size": 4096
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}
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},
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"hier_0_rtds_axis_0": {
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"reg0": {
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"baseaddr": 32768,
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"highaddr": 36863,
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"size": 4096
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}
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},
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"hier_0_hls_dft_0": {
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"Reg": {
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"baseaddr": 36864,
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"highaddr": 40959,
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"size": 4096
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}
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},
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"pcie_0_axi_pcie_intc_0": {
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"Reg": {
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"baseaddr": 45056,
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"highaddr": 49151,
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"size": 4096
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}
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},
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"pcie_0_axi_pcie_0": {
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"CTL0": {
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"baseaddr": 268435456,
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"highaddr": 536870911,
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"size": 268435456
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}
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}
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}
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},
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"axi_bars": {
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"BAR0": {
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"translation": 0,
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"baseaddr": 0,
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"highaddr": 4294967295,
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"size": 4294967296
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}
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},
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"pcie_bars": {
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"BAR0": {
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"translation": 0
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}
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}
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},
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"pcie_0_axi_pcie_intc_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0"
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},
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"pcie_0_axi_reset_0": {
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"vlnv": "xilinx.com:ip:axi_gpio:2.0"
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},
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"timer_0_axi_timer_0": {
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"vlnv": "xilinx.com:ip:axi_timer:2.0",
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"irqs": {
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"generateout0": "pcie_0_axi_pcie_intc_0:0"
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}
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}
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}
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}
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},
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"nodes": {
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"dma_0": {
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"type": "fpga",
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"datamover": "dma_0",
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"use_irqs": false
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},
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"dma_1": {
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"type": "fpga",
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"datamover": "dma_1",
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"use_irqs": false
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},
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"fifo_0": {
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"type": "fpga",
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"datamover": "fifo_mm_s_0",
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"use_irqs": false
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},
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"simple_circuit": {
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"type": "cbuilder",
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"model": "simple_circuit",
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"timestep": 2.5000000000000001e-5,
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"parameters": [
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1.0,
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0.001
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]
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}
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},
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"paths": [
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{
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"in": "dma_1",
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"out": "simple_circuit",
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"reverse": true
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}
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]
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}
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