mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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144 lines
3.6 KiB
C++
144 lines
3.6 KiB
C++
/** FPGA card
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*
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* This class represents a FPGA device.
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @author Daniel Krebs <github@daniel-krebs.net>
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* @copyright 2017-2018, Institute for Automation of Complex Power Systems, EONERC
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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/** @addtogroup fpga VILLASfpga
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* @{
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*/
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#pragma once
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#include <list>
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#include <set>
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#include <string>
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#include <jansson.h>
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#include <villas/plugin.hpp>
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#include <villas/memory.hpp>
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#include <villas/kernel/pci.h>
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#include <villas/kernel/vfio.hpp>
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#include <villas/fpga/config.h>
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#include <villas/fpga/ip.hpp>
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#define PCI_FILTER_DEFAULT_FPGA { \
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.id = { \
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.vendor = FPGA_PCI_VID_XILINX, \
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.device = FPGA_PCI_PID_VFPGA, \
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.class_code = 0 \
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}, \
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.slot = { } \
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}
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namespace villas {
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namespace fpga {
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/* Forward declarations */
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struct vfio_container;
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class PCIeCardFactory;
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class PCIeCard {
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public:
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friend PCIeCardFactory;
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PCIeCard() : filter(PCI_FILTER_DEFAULT_FPGA) {}
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~PCIeCard();
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bool init();
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bool stop() { return true; }
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bool check() { return true; }
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bool reset() { return true; }
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void dump() { }
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ip::IpCore* lookupIp(const std::string& name) const;
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ip::IpCore* lookupIp(const Vlnv& vlnv) const;
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ip::IpCore* lookupIp(const ip::IpIdentifier& id) const;
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bool
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mapMemoryBlock(const MemoryBlock& block);
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private:
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/// Cache a set of already mapped memory blocks
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std::set<MemoryManager::AddressSpaceId> memoryBlocksMapped;
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public: // TODO: make this private
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ip::IpCoreList ips; ///< IPs located on this FPGA card
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bool do_reset; /**< Reset VILLASfpga during startup? */
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int affinity; /**< Affinity for MSI interrupts */
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std::string name; /**< The name of the FPGA card */
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struct pci* pci;
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struct pci_device filter; /**< Filter for PCI device. */
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struct pci_device* pdev; /**< PCI device handle */
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/// The VFIO container that this card is part of
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std::shared_ptr<VfioContainer> vfioContainer;
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/// The VFIO device that represents this card
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VfioDevice* vfioDevice;
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/// Slave address space ID to access the PCIe address space from the FPGA
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MemoryManager::AddressSpaceId addrSpaceIdDeviceToHost;
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/// Address space identifier of the master address space of this FPGA card.
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/// This will be used for address resolution of all IPs on this card.
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MemoryManager::AddressSpaceId addrSpaceIdHostToDevice;
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protected:
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SpdLogger
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getLogger() const
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{ return loggerGetOrCreate(name); }
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SpdLogger logger;
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};
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using CardList = std::list<std::unique_ptr<PCIeCard>>;
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class PCIeCardFactory : public Plugin {
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public:
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PCIeCardFactory() :
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Plugin(Plugin::Type::FpgaCard, "FPGA Card plugin") {}
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static CardList
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make(json_t *json, struct pci* pci, std::shared_ptr<VfioContainer> vc);
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static PCIeCard*
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create();
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static SpdLogger
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getStaticLogger()
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{ return loggerGetOrCreate("PCIeCardFactory"); }
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};
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} // namespace fpga
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} // namespace villas
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/** @} */
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