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https://git.rwth-aachen.de/acs/public/villas/node/
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53 lines
1.7 KiB
C++
53 lines
1.7 KiB
C++
/** AXI PCIe bridge
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*
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* @author Daniel Krebs <github@daniel-krebs.net>
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* @copyright 2018, RWTH Institute for Automation of Complex Power Systems (ACS)
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <limits>
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#include <jansson.h>
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#include "fpga/ips/pcie.hpp"
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#include "fpga/card.hpp"
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#include "log.hpp"
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#include "memory_manager.hpp"
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namespace villas {
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namespace fpga {
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namespace ip {
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static AxiPciExpressBridgeFactory factory;
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bool
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AxiPciExpressBridge::init()
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{
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// Create an identity mapping from the FPGA card to this IP as an entry
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// point to all other IPs in the FPGA, because Vivado will generate a
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// memory view for this bridge that can see all others.
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auto addrSpace = MemoryManager::get().findAddressSpace(getInstanceName());
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MemoryManager::get().createMapping(0x00, 0x00, SIZE_MAX, "PCIeBridge",
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card->addrSpaceId, addrSpace);
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return true;
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}
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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