mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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234 lines
7.4 KiB
C++
234 lines
7.4 KiB
C++
/** FIFO unit test.
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <criterion/criterion.h>
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#include <villas/log.hpp>
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#include <villas/memory.hpp>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/ips/rtds2gpu.hpp>
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#include <villas/fpga/ips/gpu2rtds.hpp>
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#include <villas/fpga/ips/switch.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include <villas/fpga/ips/rtds.hpp>
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#include "global.hpp"
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static constexpr size_t SAMPLE_SIZE = 4;
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static constexpr size_t SAMPLE_COUNT = 1;
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static constexpr size_t FRAME_SIZE = SAMPLE_COUNT * SAMPLE_SIZE;
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static constexpr size_t DOORBELL_OFFSET = SAMPLE_COUNT;
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static constexpr size_t DATA_OFFSET = 0;
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static void dumpMem(const uint32_t* addr, size_t len)
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{
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const size_t bytesPerLine = 16;
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const size_t lines = (len) / bytesPerLine + 1;
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const uint8_t* buf = reinterpret_cast<const uint8_t*>(addr);
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size_t bytesRead = 0;
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for(size_t line = 0; line < lines; line++) {
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const unsigned base = line * bytesPerLine;
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printf("0x%04x: ", base);
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for(size_t i = 0; i < bytesPerLine && bytesRead < len; i++) {
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printf("0x%02x ", buf[base + i]);
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bytesRead++;
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}
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puts("");
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}
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}
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Test(fpga, rtds2gpu, .description = "Rtds2Gpu")
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{
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auto logger = loggerGetOrCreate("unittest:rtds2gpu");
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for(auto& ip : state.cards.front()->ips) {
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if(*ip != villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:rtds2gpu:"))
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continue;
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logger->info("Testing {}", *ip);
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/* Collect neccessary IPs */
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auto rtds2gpu = dynamic_cast<villas::fpga::ip::Rtds2Gpu&>(*ip);
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auto axiSwitch = dynamic_cast<villas::fpga::ip::AxiStreamSwitch*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("xilinx.com:ip:axis_switch:")));
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auto dma = dynamic_cast<villas::fpga::ip::Dma*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("xilinx.com:ip:axi_dma:")));
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auto gpu2rtds = dynamic_cast<villas::fpga::ip::Gpu2Rtds*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:gpu2rtds:")));
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auto rtds = dynamic_cast<villas::fpga::ip::Rtds*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")));
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cr_assert_not_null(axiSwitch, "No AXI switch IP found");
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cr_assert_not_null(dma, "No DMA IP found");
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cr_assert_not_null(gpu2rtds, "No Gpu2Rtds IP found");
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cr_assert_not_null(rtds, "RTDS IP not found");
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rtds2gpu.dump(spdlog::level::debug);
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gpu2rtds->dump(spdlog::level::debug);
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/* Allocate and prepare memory */
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// allocate space for all samples and doorbell register
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auto dmaMemSrc = villas::HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
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auto dmaMemDst = villas::HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
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auto dmaMemDst2 = villas::HostDmaRam::getAllocator(0).allocate<uint32_t>(SAMPLE_COUNT + 1);
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memset(&dmaMemSrc, 0x11, dmaMemSrc.getMemoryBlock().getSize());
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memset(&dmaMemDst, 0x55, dmaMemDst.getMemoryBlock().getSize());
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memset(&dmaMemDst2, 0x77, dmaMemDst2.getMemoryBlock().getSize());
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const uint32_t* dataSrc = &dmaMemSrc[DATA_OFFSET];
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const uint32_t* dataDst = &dmaMemDst[DATA_OFFSET];
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const uint32_t* dataDst2 = &dmaMemDst2[0];
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dumpMem(dataSrc, dmaMemSrc.getMemoryBlock().getSize());
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dumpMem(dataDst, dmaMemDst.getMemoryBlock().getSize());
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dumpMem(dataDst2, dmaMemDst2.getMemoryBlock().getSize());
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// connect AXI Stream from DMA to Rtds2Gpu IP
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cr_assert(dma->connect(rtds2gpu));
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cr_assert(rtds2gpu.startOnce(dmaMemDst.getMemoryBlock(), SAMPLE_COUNT, DATA_OFFSET * 4, DOORBELL_OFFSET * 4),
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"Preparing Rtds2Gpu IP failed");
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cr_assert(dma->write(dmaMemSrc.getMemoryBlock(), FRAME_SIZE),
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"Starting DMA MM2S transfer failed");
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cr_assert(dma->writeComplete(),
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"DMA failed");
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while(not rtds2gpu.isFinished());
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const uint32_t* doorbellDst = &dmaMemDst[DOORBELL_OFFSET];
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rtds2gpu.dump(spdlog::level::info);
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rtds2gpu.dumpDoorbell(*doorbellDst);
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cr_assert(memcmp(dataSrc, dataDst, FRAME_SIZE) == 0, "Memory not equal");
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for(size_t i = 0; i < SAMPLE_COUNT; i++) {
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gpu2rtds->registerFrames[i] = dmaMemDst[i];
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}
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// connect AXI Stream from Gpu2Rtds IP to DMA
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cr_assert(gpu2rtds->connect(*dma));
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cr_assert(dma->read(dmaMemDst2.getMemoryBlock(), FRAME_SIZE),
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"Starting DMA S2MM transfer failed");
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cr_assert(gpu2rtds->startOnce(SAMPLE_COUNT),
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"Preparing Gpu2Rtds IP failed");
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cr_assert(dma->readComplete(),
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"DMA failed");
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while(not gpu2rtds->isFinished());
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cr_assert(memcmp(dataSrc, dataDst2, FRAME_SIZE) == 0, "Memory not equal");
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dumpMem(dataSrc, dmaMemSrc.getMemoryBlock().getSize());
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dumpMem(dataDst, dmaMemDst.getMemoryBlock().getSize());
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dumpMem(dataDst2, dmaMemDst2.getMemoryBlock().getSize());
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logger->info(TXT_GREEN("Passed"));
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}
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}
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Test(fpga, rtds2gpu_rtt_cpu, .description = "Rtds2Gpu RTT via CPU")
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{
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auto logger = loggerGetOrCreate("unittest:rtds2gpu");
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/* Collect neccessary IPs */
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auto gpu2rtds = dynamic_cast<villas::fpga::ip::Gpu2Rtds*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:gpu2rtds:")));
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auto rtds2gpu = dynamic_cast<villas::fpga::ip::Rtds2Gpu*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:hls:rtds2gpu:")));
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cr_assert_not_null(gpu2rtds, "No Gpu2Rtds IP found");
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cr_assert_not_null(rtds2gpu, "No Rtds2Gpu IP not found");
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for(auto& ip : state.cards.front()->ips) {
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if(*ip != villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:"))
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continue;
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auto& rtds = dynamic_cast<villas::fpga::ip::Rtds&>(*ip);
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logger->info("Testing {}", rtds);
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auto dmaRam = villas::HostDmaRam::getAllocator().allocate<uint32_t>(SAMPLE_COUNT + 1);
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uint32_t* data = &dmaRam[DATA_OFFSET];
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uint32_t* doorbell = &dmaRam[DOORBELL_OFFSET];
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// TEST: rtds loopback via switch
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// cr_assert(rtds.connect(rtds));
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// logger->info("loopback");
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// while(1);
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cr_assert(rtds.connect(*rtds2gpu));
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cr_assert(gpu2rtds->connect(rtds));
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size_t count = 0;
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while(true) {
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rtds2gpu->doorbellReset(*doorbell);
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rtds2gpu->startOnce(dmaRam.getMemoryBlock(), SAMPLE_COUNT, DATA_OFFSET * 4, DOORBELL_OFFSET * 4);
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// while(not rtds2gpu->isFinished());
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while(not rtds2gpu->doorbellIsValid(*doorbell));
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// rtds2gpu->dump();
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// rtds2gpu->dumpDoorbell(data[1]);
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// dumpMem(data, FRAME_SIZE + SAMPLE_SIZE);
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// copy samples to gpu2rtds IP
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for(size_t i = 0; i < SAMPLE_COUNT; i++) {
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gpu2rtds->registerFrames[i] = data[i];
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}
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gpu2rtds->startOnce(SAMPLE_COUNT);
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// while(not gpu2rtds->isFinished());
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count++;
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// logger->debug("Successful iterations {}, data {}", count, data[0]);
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}
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}
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}
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