mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-30 00:00:11 +01:00
Steffen Vogel
dbc1530727
- Build RPM packages for VILLASnode and dependencies with the ‚rpm‘, ‚rpm-villas‘, ‚rpm-livxil‘ and ‚rpm-libwebsockets‘ make targets - Upload new RPM packages to the repository with the ‚deploy‘ make target - Build a developer Docker image with the `docker-dev` target - Run the developer image with the `run-docker-dev` target - Build a production Docker image with the `docker` target This requires that all RPM packages have been build previously! - Use hard-coded default paths where applicable - Updated index website - Added some usage information and hints Documentation of the new system is still outstanding
44 lines
No EOL
1.3 KiB
C
44 lines
No EOL
1.3 KiB
C
/** Static server configuration
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*
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* This file contains some compiled-in settings.
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* This settings are not part of the configuration file.
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Institute for Automation of Complex Power Systems, EONERC
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*********************************************************************************/
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#pragma once
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/** Default number of values in a sample */
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#define DEFAULT_VALUES 64
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#define DEFAULT_QUEUELEN 1024
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/** Number of hugepages which are requested from the the kernel.
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* @see https://www.kernel.org/doc/Documentation/vm/hugetlbpage.txt */
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#define DEFAULT_NR_HUGEPAGES 25
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/** Width of log output in characters */
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#define LOG_WIDTH 132
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/** Socket priority */
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#define SOCKET_PRIO 7
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/* Protocol numbers */
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#define IPPROTO_VILLAS 137
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#define ETH_P_VILLAS 0xBABE
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#define USER_AGENT "VILLASnode (" BUILDID ")"
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/*ID Required kernel version */
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#define KERNEL_VERSION_MAJ 3
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#define KERNEL_VERSION_MIN 6
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/** PCIe BAR number of VILLASfpga registers */
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#define FPGA_PCI_BAR 0
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#define FPGA_PCI_VID_XILINX 0x10ee
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#define FPGA_PCI_PID_VFPGA 0x7022
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/** AXI Bus frequency for all components
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* except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
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#define FPGA_AXI_HZ 125000000 // 125 MHz
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