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96 lines
2.8 KiB
C
96 lines
2.8 KiB
C
/** System Generator unit test.
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017-2018, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <math.h>
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#include <criterion/criterion.h>
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#include <villas/log.h>
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#include <villas/fpga/card.h>
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#include <villas/fpga/ip.h>
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#include <villas/fpga/vlnv.h>
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#include <villas/fpga/ips/dma.h>
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extern struct fpga_card *card;
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Test(fpga, xsg, .description = "XSG: multiply_add")
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{
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int ret;
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double factor, err = 0;
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struct fpga_ip *ip, *dma;
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struct model_parameter *p;
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struct dma_mem mem;
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ip = fpga_vlnv_lookup(&card->ips, &(struct fpga_vlnv) { NULL, "sysgen", "xsg_multiply", NULL });
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cr_assert(ip);
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dma = fpga_vlnv_lookup(&card->ips, &(struct fpga_vlnv) { "xilinx.com", "ip", "axi_dma", NULL });
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cr_assert(dma);
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struct model *model = (struct model *) ip->_vd;
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p = list_lookup(&model->parameters, "factor");
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if (!p)
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error("Missing parameter 'factor' for model '%s'", ip->name);
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ret = model_parameter_read(p, &factor);
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cr_assert_eq(ret, 0, "Failed to read parameter 'factor' from model '%s'", ip->name);
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info("Model param: factor = %f", factor);
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ret = switch_connect(card->sw, dma, ip);
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cr_assert_eq(ret, 0, "Failed to configure switch");
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ret = switch_connect(card->sw, ip, dma);
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cr_assert_eq(ret, 0, "Failed to configure switch");
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ret = dma_alloc(dma, &mem, 0x1000, 0);
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cr_assert_eq(ret, 0, "Failed to allocate DMA memory");
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float *src = (float *) mem.base_virt;
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float *dst = (float *) mem.base_virt + 0x800;
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for (int i = 0; i < 6; i++)
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src[i] = 1.1 * (i+1);
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ret = dma_ping_pong(dma, (char *) src, (char *) dst, 6 * sizeof(float));
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cr_assert_eq(ret, 0, "Failed to to ping pong DMA transfer: %d", ret);
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for (int i = 0; i < 6; i++)
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err += fabs(factor * src[i] - dst[i]);
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info("Error after FPGA operation: err = %f", err);
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ret = switch_disconnect(card->sw, dma, ip);
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cr_assert_eq(ret, 0, "Failed to configure switch");
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ret = switch_disconnect(card->sw, ip, dma);
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cr_assert_eq(ret, 0, "Failed to configure switch");
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ret = dma_free(dma, &mem);
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cr_assert_eq(ret, 0, "Failed to release DMA memory");
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cr_assert(err < 1e-3);
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}
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