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https://git.rwth-aachen.de/acs/public/villas/node/
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127 lines
3.3 KiB
C++
127 lines
3.3 KiB
C++
/** AXI Stream interconnect related helper functions
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*
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* These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @author Daniel Krebs <github@daniel-krebs.net>
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* @copyright 2017, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <xilinx/xaxis_switch.h>
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#include "log.hpp"
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#include "fpga/ips/switch.hpp"
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namespace villas {
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namespace fpga {
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namespace ip {
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static AxiStreamSwitchFactory factory;
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bool
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AxiStreamSwitch::start()
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{
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/* Setup AXI-stream switch */
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XAxis_Switch_Config sw_cfg;
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sw_cfg.MaxNumMI = portsMaster.size();
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sw_cfg.MaxNumSI = portsSlave.size();
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if(XAxisScr_CfgInitialize(&xSwitch, &sw_cfg, getBaseaddr()) != XST_SUCCESS) {
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return false;
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}
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/* Disable all masters */
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XAxisScr_RegUpdateDisable(&xSwitch);
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XAxisScr_MiPortDisableAll(&xSwitch);
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XAxisScr_RegUpdateEnable(&xSwitch);
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// initialize internal mapping
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for(int portMaster = 0; portMaster < portsMaster.size(); portMaster++) {
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portMapping[portMaster] = PORT_DISABLED;
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}
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return true;
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}
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bool
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AxiStreamSwitch::connect(int portSlave, int portMaster)
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{
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auto logger = getLogger();
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if(portMapping[portMaster] == portSlave) {
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logger->debug("Ports already connected");
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return true;
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}
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for(auto [master, slave] : portMapping) {
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if(slave == portSlave) {
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logger->warn("Slave {} has already been connected to master {}. "
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"Disabling master {}.",
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slave, master, master);
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XAxisScr_RegUpdateDisable(&xSwitch);
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XAxisScr_MiPortDisable(&xSwitch, master);
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XAxisScr_RegUpdateEnable(&xSwitch);
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}
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}
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/* Reconfigure switch */
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XAxisScr_RegUpdateDisable(&xSwitch);
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XAxisScr_MiPortEnable(&xSwitch, portMaster, portSlave);
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XAxisScr_RegUpdateEnable(&xSwitch);
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logger->debug("Connect slave {} to master {}", portSlave, portMaster);
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return true;
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}
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bool
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AxiStreamSwitch::disconnectMaster(int port)
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{
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auto logger = getLogger();
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logger->debug("Disconnect slave {} from master {}",
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portMapping[port], port);
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XAxisScr_MiPortDisable(&xSwitch, port);
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portMapping[port] = PORT_DISABLED;
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return true;
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}
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bool
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AxiStreamSwitch::disconnectSlave(int port)
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{
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auto logger = getLogger();
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for(auto [master, slave] : portMapping) {
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if(slave == port) {
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logger->debug("Disconnect slave {} from master {}", slave, master);
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XAxisScr_MiPortDisable(&xSwitch, master);
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return true;
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}
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}
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logger->debug("Slave {} hasn't been connected to any master", port);
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return true;
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}
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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