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https://git.rwth-aachen.de/acs/public/villas/node/
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118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
/** AXI-PCIe Interrupt controller
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2015-2016, Steffen Vogel
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* This file is part of S2SS. All Rights Reserved. Proprietary and confidential.
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* Unauthorized copying of this file, via any medium is strictly prohibited.
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**********************************************************************************/
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#include <unistd.h>
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#include "log.h"
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#include "nodes/fpga.h"
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#include "kernel/vfio.h"
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#include "fpga/ip.h"
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#include "fpga/intc.h"
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int intc_init(struct ip *c)
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{
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struct fpga *f = c->card;
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int ret;
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if (c != f->intc)
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error("There can be only one interrupt controller per FPGA");
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uintptr_t base = (uintptr_t) f->map + c->baseaddr;
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/* Setup IRQs */
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for (int i = 0; i < f->vd.irqs[VFIO_PCI_MSI_IRQ_INDEX].count; i++) {
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/* Setup vector */
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XIntc_Out32(base + XIN_IVAR_OFFSET + i * 4, i);
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/* Register eventfd with VFIO */
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ret = vfio_pci_msi_fd(&f->vd, (1 << i));
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if (ret < 0)
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serror("Failed to create eventfd for IRQ: ret=%d", f->vd.msi_efds[i]);
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}
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XIntc_Out32(base + XIN_IMR_OFFSET, 0); /* Use manual acknowlegement for all IRQs */
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XIntc_Out32(base + XIN_IAR_OFFSET, 0xFFFFFFFF); /* Acknowlege all pending IRQs manually */
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XIntc_Out32(base + XIN_IMR_OFFSET, 0xFFFFFFFF); /* Use fast acknowlegement for all IRQs */
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XIntc_Out32(base + XIN_IER_OFFSET, 0x00000000); /* Disable all IRQs by default */
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XIntc_Out32(base + XIN_MER_OFFSET, XIN_INT_HARDWARE_ENABLE_MASK | XIN_INT_MASTER_ENABLE_MASK);
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debug(4, "FPGA: enabled interrupts");
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return 0;
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}
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int intc_enable(struct ip *c, uint32_t mask, int poll)
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{
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struct fpga *f = c->card;
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uint32_t ier, imr;
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uintptr_t base = (uintptr_t) f->map + c->baseaddr;
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/* Current state of INTC */
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ier = XIntc_In32(base + XIN_IER_OFFSET);
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imr = XIntc_In32(base + XIN_IMR_OFFSET);
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/* Clear pending IRQs */
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XIntc_Out32(base + XIN_IAR_OFFSET, mask);
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if (poll)
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XIntc_Out32(base + XIN_IMR_OFFSET, imr & ~mask);
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else
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XIntc_Out32(base + XIN_IER_OFFSET, ier | mask);
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debug(8, "FPGA: Interupt enabled: %#x", mask);
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return 0;
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}
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int intc_disable(struct ip *c, uint32_t mask)
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{
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struct fpga *f = c->card;
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uintptr_t base = (uintptr_t) f->map + c->baseaddr;
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XIntc_Out32(base + XIN_IER_OFFSET, XIntc_In32(base + XIN_IER_OFFSET) & ~mask);
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return 0;
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}
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uint64_t intc_wait(struct ip *c, int irq, int poll)
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{
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struct fpga *f = c->card;
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uintptr_t base = (uintptr_t) f->map + c->baseaddr;
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uint64_t cnt;
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if (poll) {
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uint32_t mask = 1 << irq;
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uint32_t isr;
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do { /* Wait for IRQ to occur */
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isr = XIntc_In32(base + XIN_ISR_OFFSET);
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} while (!(isr & mask));
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/* Acknowlege */
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XIntc_Out32(base + XIN_IAR_OFFSET, mask);
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cnt = 1;
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}
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else {
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ssize_t ret = read(f->vd.msi_efds[irq], &cnt, sizeof(cnt));
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if (ret != sizeof(cnt))
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return 0;
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}
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return cnt;
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}
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static struct ip_type ip = {
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.vlnv = { "acs.eonerc.rwth-aachen.de", "user", "axi_pcie_intc", NULL },
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.init = intc_init
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};
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REGISTER_IP_TYPE(&ip)
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