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https://git.rwth-aachen.de/acs/public/villas/node/
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46 lines
No EOL
2.1 KiB
C
46 lines
No EOL
2.1 KiB
C
/** Driver for AXI Stream wrapper around RTDS_InterfaceModule (rtds_axis )
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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**********************************************************************************/
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/** @addtogroup fpga VILLASfpga
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* @{
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*/
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#pragma once
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/* Forward declarations */
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struct ip;
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#define RTDS_HZ 100000000 // 100 MHz
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#define RTDS_AXIS_MAX_TX 64 /**< The amount of values which is supported by the vfpga card */
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#define RTDS_AXIS_MAX_RX 64 /**< The amount of values which is supported by the vfpga card */
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/* Register offsets */
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#define RTDS_AXIS_SR_OFFSET 0x00 /**< Status Register (read-only). See RTDS_AXIS_SR_* constant. */
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#define RTDS_AXIS_CR_OFFSET 0x04 /**< Control Register (read/write) */
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#define RTDS_AXIS_TSCNT_LOW_OFFSET 0x08 /**< Lower 32 bits of timestep counter (read-only). */
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#define RTDS_AXIS_TSCNT_HIGH_OFFSET 0x0C /**< Higher 32 bits of timestep counter (read-only). */
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#define RTDS_AXIS_TS_PERIOD_OFFSET 0x10 /**< Period in clock cycles of previous timestep (read-only). */
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#define RTDS_AXIS_COALESC_OFFSET 0x14 /**< IRQ Coalescing register (read/write). */
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#define RTDS_AXIS_VERSION_OFFSET 0x18 /**< 16 bit version field passed back to the rack for version reporting (visible from “status” command, read/write). */
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#define RTDS_AXIS_MRATE 0x1C /**< Multi-rate register */
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/* Status register bits */
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#define RTDS_AXIS_SR_CARDDETECTED (1 << 0)/**< ‘1’ when RTDS software has detected and configured card. */
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#define RTDS_AXIS_SR_LINKUP (1 << 1)/**< ‘1’ when RTDS communication link has been negotiated. */
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#define RTDS_AXIS_SR_TX_FULL (1 << 2)/**< Tx buffer is full, writes that happen when UserTxFull=’1’ will be dropped (Throttling / buffering is performed by hardware). */
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#define RTDS_AXIS_SR_TX_INPROGRESS (1 << 3)/**< Indicates when data is being put on link. */
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#define RTDS_AXIS_SR_CASE_RUNNING (1 << 4)/**< There is currently a simulation running. */
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/* Control register bits */
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#define RTDS_AXIS_CR_DISABLE_LINK 0 /**< Disable SFP TX when set */
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void rtds_axis_dump(struct fpga_ip *c);
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double rtds_axis_dt(struct fpga_ip *c);
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/** @} */ |