Niklas Eiling 9cf926d84e fpga: add lowLatencyMode setting ... This setting improves latency by remove various checks. Use with caution! Requires read cache in FPGA design! The common use case in VILLASfpga is that we have exactly one write for every read and the number of exchanged signals do not change. If this is the case, we can reuse the buffer descriptors during reads and write, thus avoidng freeing, reallocating and setting them up. We set up the descriptors in start, and in write or read, we only reset the complete bit in the buffer descriptor and write to the tdesc register to start the DMA transfer. Improves read/write latency by approx. 40%. Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>		2024-04-19 10:09:47 +02:00
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villas	fpga: add lowLatencyMode setting	2024-04-19 10:09:47 +02:00