mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-09 00:00:00 +01:00
1379 lines
39 KiB
JSON
1379 lines
39 KiB
JSON
{
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"aurora_aurora_8b10b_ch0": {
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"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
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"parameters": {
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"component_name": "design_1_aurora_8b10b_0_0",
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"channel_enable": "X0Y0",
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"c_refclk_loc_p": "BL8",
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"c_refclk_loc_n": "BL7",
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"c_column_used": "right",
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"c_ucolumn_used": "right",
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"c_family": "virtex7",
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|
"c_device": "xc7vx485t",
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"c_row_used": "None",
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"c_xpackage": "ffg1761",
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"c_xspeedgrade": -2,
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"c_aurora_lanes": 1,
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"c_lane_width": 4,
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"c_active_transceiverquads": 1,
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"c_start_quad": "X0Y0",
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"c_start_lane": "X0Y0",
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"c_refclk_source": "none",
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"interface_mode": "Framing",
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"c_stream": "false",
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"dataflow_config": "Duplex",
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"backchannel_mode": "Sidebands",
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"c_simplex": "false",
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"c_simplex_mode": "TX",
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"flow_mode": "None",
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|
"c_nfc": "false",
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"c_nfc_mode": "IMM",
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"c_ufc": "false",
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"c_example_simulation": "false",
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|
"c_gtwiz_out": "false",
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"c_line_rate": 2,
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"cc_line_rate": 2,
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"c_refclk_frequency": "250.000",
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"cc_refclk_frequency": "250.000",
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"c_init_clk": "100.0",
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"drp_freq": "100.0",
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"c_gt_loc_1": 1,
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"c_gt_loc_2": "X",
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"c_gt_loc_3": "X",
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"c_gt_loc_4": "X",
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"c_gt_loc_5": "X",
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"c_gt_loc_6": "X",
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"c_gt_loc_7": "X",
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"c_gt_loc_8": "X",
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"c_gt_loc_9": "X",
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"c_gt_loc_10": "X",
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|
"c_gt_loc_11": "X",
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|
"c_gt_loc_12": "X",
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|
"c_gt_loc_13": "X",
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"c_gt_loc_14": "X",
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"c_gt_loc_15": "X",
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"c_gt_loc_16": "X",
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|
"c_gt_loc_17": "X",
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|
"c_gt_loc_18": "X",
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"c_gt_loc_19": "X",
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"c_gt_loc_20": "X",
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"c_gt_loc_21": "X",
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"c_gt_loc_22": "X",
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"c_gt_loc_23": "X",
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"c_gt_loc_24": "X",
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"c_gt_loc_25": "X",
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"c_gt_loc_26": "X",
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"c_gt_loc_27": "X",
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"c_gt_loc_28": "X",
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"c_gt_loc_29": "X",
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"c_gt_loc_30": "X",
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"c_gt_loc_31": "X",
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"c_gt_loc_32": "X",
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"c_gt_loc_33": "X",
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"c_gt_loc_34": "X",
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"c_gt_loc_35": "X",
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"c_gt_loc_36": "X",
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"c_gt_loc_37": "X",
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"c_gt_loc_38": "X",
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"c_gt_loc_39": "X",
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"c_gt_loc_40": "X",
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"c_gt_loc_41": "X",
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"c_gt_loc_42": "X",
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"c_gt_loc_43": "X",
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"c_gt_loc_44": "X",
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"c_gt_loc_45": "X",
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"c_gt_loc_46": "X",
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"c_gt_loc_47": "X",
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"c_gt_loc_48": "X",
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"c_gt_clock_1": "GTXQ0",
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"c_gt_clock_2": "None",
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"c_use_scrambler": "false",
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"c_use_chipscope": "false",
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"c_drp_if": "false",
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"transceivercontrol": "false",
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"c_use_crc": "true",
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"supportlevel": 1,
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"c_use_byteswap": "false",
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"c_cpll_fbdiv": 2,
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"c_cpll_fbdiv_45": 4,
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"c_cpll_refclk_div": 1,
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"c_rxoutdiv": 2,
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"c_txoutdiv": 2,
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"user_interface": "AXI_4_Streaming",
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"c_ufcbuswidthselect": 32,
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"c_ufcrembuswidthselect": 2,
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"c_ufcstrbbuswidthselect": 4,
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"c_rembuswidthselect": 2,
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"isv7gth": "false",
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"gtquadcnt": 1,
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"port7dmonitorout": 7,
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"is_7series": "true",
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"singleend_initclk": "true",
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"singleend_gtrefclk": "true",
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"c_double_gtrxreset": "false",
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"c_doccport_enable": "false",
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"is_board": "vc707",
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"usdrpaddr_width": 8,
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"usdmon_width": 16,
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"txdiffctrl_width": 3,
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"ins_loss_nyq": 14,
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"rx_eq_mode": "AUTO",
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"rx_coupling": "AC",
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"rx_termination": "PROGRAMMABLE",
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"rx_termination_prog_value": 800,
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"rx_ppm_offset": 200,
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"edk_iptype": "PERIPHERAL"
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},
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"ports": [
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{
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"role": "master",
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"target": "crossbar_axis_interconnect_0_xbar:S00_AXIS",
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"name": "USER_DATA_M_AXI_RX"
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},
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{
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"role": "slave",
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"target": "crossbar_axis_interconnect_0_xbar:M00_AXIS",
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"name": "USER_DATA_S_AXI_TX"
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}
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]
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},
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"aurora_aurora_8b10b_ch1": {
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"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
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"parameters": {
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"component_name": "design_1_aurora_8b10b_1_0",
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"channel_enable": "X0Y0",
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"c_refclk_loc_p": "BL8",
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"c_refclk_loc_n": "BL7",
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"c_column_used": "right",
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"c_ucolumn_used": "right",
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"c_family": "virtex7",
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"c_device": "xc7vx485t",
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"c_row_used": "None",
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"c_xpackage": "ffg1761",
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"c_xspeedgrade": -2,
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"c_aurora_lanes": 1,
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"c_lane_width": 4,
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"c_active_transceiverquads": 1,
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"c_start_quad": "X0Y0",
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"c_start_lane": "X0Y0",
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"c_refclk_source": "none",
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"interface_mode": "Framing",
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"c_stream": "false",
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"dataflow_config": "Duplex",
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"backchannel_mode": "Sidebands",
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"c_simplex": "false",
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"c_simplex_mode": "TX",
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"flow_mode": "None",
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"c_nfc": "false",
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"c_nfc_mode": "IMM",
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"c_ufc": "false",
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"c_example_simulation": "false",
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"c_gtwiz_out": "false",
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"c_line_rate": 2,
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"cc_line_rate": 2,
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"c_refclk_frequency": "250.000",
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"cc_refclk_frequency": "250.000",
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"c_init_clk": "100.0",
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"drp_freq": "100.0",
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"c_gt_loc_1": 1,
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"c_gt_loc_2": "X",
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"c_gt_loc_3": "X",
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"c_gt_loc_4": "X",
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"c_gt_loc_5": "X",
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"c_gt_loc_6": "X",
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"c_gt_loc_7": "X",
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"c_gt_loc_8": "X",
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"c_gt_loc_9": "X",
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"c_gt_loc_10": "X",
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"c_gt_loc_11": "X",
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"c_gt_loc_12": "X",
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"c_gt_loc_13": "X",
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"c_gt_loc_14": "X",
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"c_gt_loc_15": "X",
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"c_gt_loc_16": "X",
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"c_gt_loc_17": "X",
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"c_gt_loc_18": "X",
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"c_gt_loc_19": "X",
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"c_gt_loc_20": "X",
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"c_gt_loc_21": "X",
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"c_gt_loc_22": "X",
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"c_gt_loc_23": "X",
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"c_gt_loc_24": "X",
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"c_gt_loc_25": "X",
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"c_gt_loc_26": "X",
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"c_gt_loc_27": "X",
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"c_gt_loc_28": "X",
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"c_gt_loc_29": "X",
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"c_gt_loc_30": "X",
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"c_gt_loc_31": "X",
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"c_gt_loc_32": "X",
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"c_gt_loc_33": "X",
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"c_gt_loc_34": "X",
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"c_gt_loc_35": "X",
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"c_gt_loc_36": "X",
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"c_gt_loc_37": "X",
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"c_gt_loc_38": "X",
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"c_gt_loc_39": "X",
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"c_gt_loc_40": "X",
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"c_gt_loc_41": "X",
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"c_gt_loc_42": "X",
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"c_gt_loc_43": "X",
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"c_gt_loc_44": "X",
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"c_gt_loc_45": "X",
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"c_gt_loc_46": "X",
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"c_gt_loc_47": "X",
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"c_gt_loc_48": "X",
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"c_gt_clock_1": "GTXQ0",
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"c_gt_clock_2": "None",
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"c_use_scrambler": "false",
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"c_use_chipscope": "false",
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"c_drp_if": "false",
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"transceivercontrol": "false",
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"c_use_crc": "false",
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"supportlevel": 0,
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"c_use_byteswap": "false",
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"c_cpll_fbdiv": 2,
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"c_cpll_fbdiv_45": 4,
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"c_cpll_refclk_div": 1,
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"c_rxoutdiv": 2,
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"c_txoutdiv": 2,
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"user_interface": "AXI_4_Streaming",
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"c_ufcbuswidthselect": 32,
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"c_ufcrembuswidthselect": 2,
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"c_ufcstrbbuswidthselect": 4,
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"c_rembuswidthselect": 2,
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"isv7gth": "false",
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"gtquadcnt": 1,
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"port7dmonitorout": 7,
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"is_7series": "true",
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"singleend_initclk": "false",
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"singleend_gtrefclk": "false",
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"c_double_gtrxreset": "false",
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"c_doccport_enable": "false",
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"is_board": "vc707",
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"usdrpaddr_width": 8,
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"usdmon_width": 16,
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"txdiffctrl_width": 3,
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"ins_loss_nyq": 14,
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"rx_eq_mode": "AUTO",
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"rx_coupling": "AC",
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"rx_termination": "PROGRAMMABLE",
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"rx_termination_prog_value": 800,
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"rx_ppm_offset": 200,
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"edk_iptype": "PERIPHERAL"
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},
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"ports": [
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{
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"role": "master",
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"target": "crossbar_axis_interconnect_0_xbar:S01_AXIS",
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"name": "USER_DATA_M_AXI_RX"
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},
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{
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"role": "slave",
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"target": "crossbar_axis_interconnect_0_xbar:M01_AXIS",
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"name": "USER_DATA_S_AXI_TX"
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}
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]
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},
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"aurora_aurora_8b10b_ch2": {
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"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
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"parameters": {
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"component_name": "design_1_aurora_8b10b_3_0",
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"channel_enable": "X0Y0",
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"c_refclk_loc_p": "BL8",
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"c_refclk_loc_n": "BL7",
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"c_column_used": "right",
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"c_ucolumn_used": "right",
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"c_family": "virtex7",
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"c_device": "xc7vx485t",
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"c_row_used": "None",
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"c_xpackage": "ffg1761",
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"c_xspeedgrade": -2,
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"c_aurora_lanes": 1,
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"c_lane_width": 4,
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"c_active_transceiverquads": 1,
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"c_start_quad": "X0Y0",
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"c_start_lane": "X0Y0",
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"c_refclk_source": "none",
|
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"interface_mode": "Framing",
|
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"c_stream": "false",
|
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"dataflow_config": "Duplex",
|
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"backchannel_mode": "Sidebands",
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"c_simplex": "false",
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"c_simplex_mode": "TX",
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"flow_mode": "None",
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"c_nfc": "false",
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"c_nfc_mode": "IMM",
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"c_ufc": "false",
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"c_example_simulation": "false",
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"c_gtwiz_out": "false",
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"c_line_rate": 2,
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"cc_line_rate": 2,
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"c_refclk_frequency": "250.000",
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"cc_refclk_frequency": "250.000",
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"c_init_clk": "100.0",
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"drp_freq": "100.0",
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"c_gt_loc_1": "X",
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"c_gt_loc_2": "X",
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"c_gt_loc_3": "X",
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"c_gt_loc_4": "X",
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"c_gt_loc_5": "X",
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"c_gt_loc_6": "X",
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"c_gt_loc_7": "X",
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"c_gt_loc_8": "X",
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"c_gt_loc_9": "X",
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"c_gt_loc_10": "X",
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"c_gt_loc_11": "X",
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"c_gt_loc_12": "X",
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|
"c_gt_loc_13": "X",
|
|
"c_gt_loc_14": "X",
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"c_gt_loc_15": "X",
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"c_gt_loc_16": "X",
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"c_gt_loc_17": "X",
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"c_gt_loc_18": "X",
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"c_gt_loc_19": "X",
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|
"c_gt_loc_20": "X",
|
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"c_gt_loc_21": "X",
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"c_gt_loc_22": "X",
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"c_gt_loc_23": "X",
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"c_gt_loc_24": "X",
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"c_gt_loc_25": "X",
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"c_gt_loc_26": 1,
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"c_gt_loc_27": "X",
|
|
"c_gt_loc_28": "X",
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|
"c_gt_loc_29": "X",
|
|
"c_gt_loc_30": "X",
|
|
"c_gt_loc_31": "X",
|
|
"c_gt_loc_32": "X",
|
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"c_gt_loc_33": "X",
|
|
"c_gt_loc_34": "X",
|
|
"c_gt_loc_35": "X",
|
|
"c_gt_loc_36": "X",
|
|
"c_gt_loc_37": "X",
|
|
"c_gt_loc_38": "X",
|
|
"c_gt_loc_39": "X",
|
|
"c_gt_loc_40": "X",
|
|
"c_gt_loc_41": "X",
|
|
"c_gt_loc_42": "X",
|
|
"c_gt_loc_43": "X",
|
|
"c_gt_loc_44": "X",
|
|
"c_gt_loc_45": "X",
|
|
"c_gt_loc_46": "X",
|
|
"c_gt_loc_47": "X",
|
|
"c_gt_loc_48": "X",
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"c_gt_clock_1": "GTXQ6",
|
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"c_gt_clock_2": "None",
|
|
"c_use_scrambler": "false",
|
|
"c_use_chipscope": "false",
|
|
"c_drp_if": "false",
|
|
"transceivercontrol": "false",
|
|
"c_use_crc": "false",
|
|
"supportlevel": 0,
|
|
"c_use_byteswap": "false",
|
|
"c_cpll_fbdiv": 2,
|
|
"c_cpll_fbdiv_45": 4,
|
|
"c_cpll_refclk_div": 1,
|
|
"c_rxoutdiv": 2,
|
|
"c_txoutdiv": 2,
|
|
"user_interface": "AXI_4_Streaming",
|
|
"c_ufcbuswidthselect": 32,
|
|
"c_ufcrembuswidthselect": 2,
|
|
"c_ufcstrbbuswidthselect": 4,
|
|
"c_rembuswidthselect": 2,
|
|
"isv7gth": "false",
|
|
"gtquadcnt": 1,
|
|
"port7dmonitorout": 7,
|
|
"is_7series": "true",
|
|
"singleend_initclk": "false",
|
|
"singleend_gtrefclk": "false",
|
|
"c_double_gtrxreset": "false",
|
|
"c_doccport_enable": "false",
|
|
"is_board": "vc707",
|
|
"usdrpaddr_width": 8,
|
|
"usdmon_width": 16,
|
|
"txdiffctrl_width": 3,
|
|
"ins_loss_nyq": 14,
|
|
"rx_eq_mode": "AUTO",
|
|
"rx_coupling": "AC",
|
|
"rx_termination": "PROGRAMMABLE",
|
|
"rx_termination_prog_value": 800,
|
|
"rx_ppm_offset": 200,
|
|
"edk_iptype": "PERIPHERAL"
|
|
},
|
|
"ports": [
|
|
{
|
|
"role": "master",
|
|
"target": "crossbar_axis_interconnect_0_xbar:S02_AXIS",
|
|
"name": "USER_DATA_M_AXI_RX"
|
|
},
|
|
{
|
|
"role": "slave",
|
|
"target": "crossbar_axis_interconnect_0_xbar:M02_AXIS",
|
|
"name": "USER_DATA_S_AXI_TX"
|
|
}
|
|
]
|
|
},
|
|
"aurora_aurora_8b10b_ch3": {
|
|
"vlnv": "xilinx.com:ip:aurora_8b10b:11.1",
|
|
"parameters": {
|
|
"component_name": "design_1_aurora_8b10b_2_0",
|
|
"channel_enable": "X0Y0",
|
|
"c_refclk_loc_p": "BL8",
|
|
"c_refclk_loc_n": "BL7",
|
|
"c_column_used": "right",
|
|
"c_ucolumn_used": "right",
|
|
"c_family": "virtex7",
|
|
"c_device": "xc7vx485t",
|
|
"c_row_used": "None",
|
|
"c_xpackage": "ffg1761",
|
|
"c_xspeedgrade": -2,
|
|
"c_aurora_lanes": 1,
|
|
"c_lane_width": 4,
|
|
"c_active_transceiverquads": 1,
|
|
"c_start_quad": "X0Y0",
|
|
"c_start_lane": "X0Y0",
|
|
"c_refclk_source": "none",
|
|
"interface_mode": "Framing",
|
|
"c_stream": "false",
|
|
"dataflow_config": "Duplex",
|
|
"backchannel_mode": "Sidebands",
|
|
"c_simplex": "false",
|
|
"c_simplex_mode": "TX",
|
|
"flow_mode": "None",
|
|
"c_nfc": "false",
|
|
"c_nfc_mode": "IMM",
|
|
"c_ufc": "false",
|
|
"c_example_simulation": "false",
|
|
"c_gtwiz_out": "false",
|
|
"c_line_rate": 2,
|
|
"cc_line_rate": 2,
|
|
"c_refclk_frequency": "250.000",
|
|
"cc_refclk_frequency": "250.000",
|
|
"c_init_clk": "100.0",
|
|
"drp_freq": "100.0",
|
|
"c_gt_loc_1": "X",
|
|
"c_gt_loc_2": "X",
|
|
"c_gt_loc_3": "X",
|
|
"c_gt_loc_4": "X",
|
|
"c_gt_loc_5": "X",
|
|
"c_gt_loc_6": "X",
|
|
"c_gt_loc_7": "X",
|
|
"c_gt_loc_8": "X",
|
|
"c_gt_loc_9": "X",
|
|
"c_gt_loc_10": "X",
|
|
"c_gt_loc_11": "X",
|
|
"c_gt_loc_12": "X",
|
|
"c_gt_loc_13": "X",
|
|
"c_gt_loc_14": "X",
|
|
"c_gt_loc_15": "X",
|
|
"c_gt_loc_16": "X",
|
|
"c_gt_loc_17": "X",
|
|
"c_gt_loc_18": "X",
|
|
"c_gt_loc_19": "X",
|
|
"c_gt_loc_20": "X",
|
|
"c_gt_loc_21": "X",
|
|
"c_gt_loc_22": "X",
|
|
"c_gt_loc_23": "X",
|
|
"c_gt_loc_24": "X",
|
|
"c_gt_loc_25": 1,
|
|
"c_gt_loc_26": "X",
|
|
"c_gt_loc_27": "X",
|
|
"c_gt_loc_28": "X",
|
|
"c_gt_loc_29": "X",
|
|
"c_gt_loc_30": "X",
|
|
"c_gt_loc_31": "X",
|
|
"c_gt_loc_32": "X",
|
|
"c_gt_loc_33": "X",
|
|
"c_gt_loc_34": "X",
|
|
"c_gt_loc_35": "X",
|
|
"c_gt_loc_36": "X",
|
|
"c_gt_loc_37": "X",
|
|
"c_gt_loc_38": "X",
|
|
"c_gt_loc_39": "X",
|
|
"c_gt_loc_40": "X",
|
|
"c_gt_loc_41": "X",
|
|
"c_gt_loc_42": "X",
|
|
"c_gt_loc_43": "X",
|
|
"c_gt_loc_44": "X",
|
|
"c_gt_loc_45": "X",
|
|
"c_gt_loc_46": "X",
|
|
"c_gt_loc_47": "X",
|
|
"c_gt_loc_48": "X",
|
|
"c_gt_clock_1": "GTXQ6",
|
|
"c_gt_clock_2": "None",
|
|
"c_use_scrambler": "false",
|
|
"c_use_chipscope": "false",
|
|
"c_drp_if": "false",
|
|
"transceivercontrol": "false",
|
|
"c_use_crc": "false",
|
|
"supportlevel": 0,
|
|
"c_use_byteswap": "false",
|
|
"c_cpll_fbdiv": 2,
|
|
"c_cpll_fbdiv_45": 4,
|
|
"c_cpll_refclk_div": 1,
|
|
"c_rxoutdiv": 2,
|
|
"c_txoutdiv": 2,
|
|
"user_interface": "AXI_4_Streaming",
|
|
"c_ufcbuswidthselect": 32,
|
|
"c_ufcrembuswidthselect": 2,
|
|
"c_ufcstrbbuswidthselect": 4,
|
|
"c_rembuswidthselect": 2,
|
|
"isv7gth": "false",
|
|
"gtquadcnt": 1,
|
|
"port7dmonitorout": 7,
|
|
"is_7series": "true",
|
|
"singleend_initclk": "false",
|
|
"singleend_gtrefclk": "false",
|
|
"c_double_gtrxreset": "false",
|
|
"c_doccport_enable": "false",
|
|
"is_board": "vc707",
|
|
"usdrpaddr_width": 8,
|
|
"usdmon_width": 16,
|
|
"txdiffctrl_width": 3,
|
|
"ins_loss_nyq": 14,
|
|
"rx_eq_mode": "AUTO",
|
|
"rx_coupling": "AC",
|
|
"rx_termination": "PROGRAMMABLE",
|
|
"rx_termination_prog_value": 800,
|
|
"rx_ppm_offset": 200,
|
|
"edk_iptype": "PERIPHERAL"
|
|
},
|
|
"ports": [
|
|
{
|
|
"role": "master",
|
|
"target": "crossbar_axis_interconnect_0_xbar:S03_AXIS",
|
|
"name": "USER_DATA_M_AXI_RX"
|
|
},
|
|
{
|
|
"role": "slave",
|
|
"target": "crossbar_axis_interconnect_0_xbar:M03_AXIS",
|
|
"name": "USER_DATA_S_AXI_TX"
|
|
}
|
|
]
|
|
},
|
|
"axi_gpio_0": {
|
|
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
|
"parameters": {
|
|
"c_family": "virtex7",
|
|
"c_s_axi_addr_width": 9,
|
|
"c_s_axi_data_width": 32,
|
|
"c_gpio_width": 8,
|
|
"c_gpio2_width": 32,
|
|
"c_all_inputs": 0,
|
|
"c_all_inputs_2": 0,
|
|
"c_all_outputs": 1,
|
|
"c_all_outputs_2": 0,
|
|
"c_interrupt_present": 0,
|
|
"c_dout_default": 0,
|
|
"c_tri_default": 4294967295,
|
|
"c_is_dual": 0,
|
|
"c_dout_default_2": 0,
|
|
"c_tri_default_2": 4294967295,
|
|
"component_name": "design_1_axi_gpio_0_0",
|
|
"use_board_flow": "false",
|
|
"gpio_board_interface": "led_8bits",
|
|
"gpio2_board_interface": "Custom",
|
|
"edk_iptype": "PERIPHERAL",
|
|
"c_baseaddr": 0,
|
|
"c_highaddr": 127
|
|
}
|
|
},
|
|
"crossbar_axis_interconnect_0_xbar": {
|
|
"vlnv": "xilinx.com:ip:axis_switch:1.1",
|
|
"parameters": {
|
|
"c_family": "virtex7",
|
|
"c_num_si_slots": 6,
|
|
"c_log_si_slots": 3,
|
|
"c_num_mi_slots": 6,
|
|
"c_axis_tdata_width": 32,
|
|
"c_axis_tid_width": 1,
|
|
"c_axis_tdest_width": 1,
|
|
"c_axis_tuser_width": 1,
|
|
"c_axis_signal_set": 27,
|
|
"c_arb_on_max_xfers": 1,
|
|
"c_arb_on_num_cycles": 0,
|
|
"c_arb_on_tlast": 0,
|
|
"c_include_arbiter": 1,
|
|
"c_arb_algorithm": 0,
|
|
"c_output_reg": 0,
|
|
"c_decoder_reg": 1,
|
|
"c_m_axis_connectivity_array": 68719476735,
|
|
"c_m_axis_basetdest_array": 42,
|
|
"c_m_axis_hightdest_array": 42,
|
|
"c_routing_mode": 1,
|
|
"c_s_axi_ctrl_addr_width": 7,
|
|
"c_s_axi_ctrl_data_width": 32,
|
|
"c_common_clock": 0,
|
|
"num_si": 6,
|
|
"num_mi": 6,
|
|
"routing_mode": 1,
|
|
"has_tready": 1,
|
|
"tdata_num_bytes": 4,
|
|
"has_tstrb": 0,
|
|
"has_tkeep": 1,
|
|
"has_tlast": 1,
|
|
"tid_width": 0,
|
|
"tdest_width": 0,
|
|
"tuser_width": 0,
|
|
"has_aclken": 0,
|
|
"arb_on_max_xfers": 1,
|
|
"arb_on_num_cycles": 0,
|
|
"arb_on_tlast": 0,
|
|
"arb_algorithm": 0,
|
|
"decoder_reg": 1,
|
|
"output_reg": 0,
|
|
"common_clock": 0,
|
|
"m00_axis_basetdest": 0,
|
|
"m01_axis_basetdest": 1,
|
|
"m02_axis_basetdest": 2,
|
|
"m03_axis_basetdest": 3,
|
|
"m04_axis_basetdest": 4,
|
|
"m05_axis_basetdest": 5,
|
|
"m06_axis_basetdest": 6,
|
|
"m07_axis_basetdest": 7,
|
|
"m08_axis_basetdest": 8,
|
|
"m09_axis_basetdest": 9,
|
|
"m10_axis_basetdest": 10,
|
|
"m11_axis_basetdest": 11,
|
|
"m12_axis_basetdest": 12,
|
|
"m13_axis_basetdest": 13,
|
|
"m14_axis_basetdest": 14,
|
|
"m15_axis_basetdest": 15,
|
|
"m00_axis_hightdest": 0,
|
|
"m01_axis_hightdest": 1,
|
|
"m02_axis_hightdest": 2,
|
|
"m03_axis_hightdest": 3,
|
|
"m04_axis_hightdest": 4,
|
|
"m05_axis_hightdest": 5,
|
|
"m06_axis_hightdest": 6,
|
|
"m07_axis_hightdest": 7,
|
|
"m08_axis_hightdest": 8,
|
|
"m09_axis_hightdest": 9,
|
|
"m10_axis_hightdest": 10,
|
|
"m11_axis_hightdest": 11,
|
|
"m12_axis_hightdest": 12,
|
|
"m13_axis_hightdest": 13,
|
|
"m14_axis_hightdest": 14,
|
|
"m15_axis_hightdest": 15,
|
|
"m00_s00_connectivity": 1,
|
|
"m00_s01_connectivity": 1,
|
|
"m00_s02_connectivity": 1,
|
|
"m00_s03_connectivity": 1,
|
|
"m00_s04_connectivity": 1,
|
|
"m00_s05_connectivity": 1,
|
|
"m00_s06_connectivity": 1,
|
|
"m00_s07_connectivity": 1,
|
|
"m00_s08_connectivity": 1,
|
|
"m00_s09_connectivity": 1,
|
|
"m00_s10_connectivity": 1,
|
|
"m00_s11_connectivity": 1,
|
|
"m00_s12_connectivity": 1,
|
|
"m00_s13_connectivity": 1,
|
|
"m00_s14_connectivity": 1,
|
|
"m00_s15_connectivity": 1,
|
|
"m01_s00_connectivity": 1,
|
|
"m01_s01_connectivity": 1,
|
|
"m01_s02_connectivity": 1,
|
|
"m01_s03_connectivity": 1,
|
|
"m01_s04_connectivity": 1,
|
|
"m01_s05_connectivity": 1,
|
|
"m01_s06_connectivity": 1,
|
|
"m01_s07_connectivity": 1,
|
|
"m01_s08_connectivity": 1,
|
|
"m01_s09_connectivity": 1,
|
|
"m01_s10_connectivity": 1,
|
|
"m01_s11_connectivity": 1,
|
|
"m01_s12_connectivity": 1,
|
|
"m01_s13_connectivity": 1,
|
|
"m01_s14_connectivity": 1,
|
|
"m01_s15_connectivity": 1,
|
|
"m02_s00_connectivity": 1,
|
|
"m02_s01_connectivity": 1,
|
|
"m02_s02_connectivity": 1,
|
|
"m02_s03_connectivity": 1,
|
|
"m02_s04_connectivity": 1,
|
|
"m02_s05_connectivity": 1,
|
|
"m02_s06_connectivity": 1,
|
|
"m02_s07_connectivity": 1,
|
|
"m02_s08_connectivity": 1,
|
|
"m02_s09_connectivity": 1,
|
|
"m02_s10_connectivity": 1,
|
|
"m02_s11_connectivity": 1,
|
|
"m02_s12_connectivity": 1,
|
|
"m02_s13_connectivity": 1,
|
|
"m02_s14_connectivity": 1,
|
|
"m02_s15_connectivity": 1,
|
|
"m03_s00_connectivity": 1,
|
|
"m03_s01_connectivity": 1,
|
|
"m03_s02_connectivity": 1,
|
|
"m03_s03_connectivity": 1,
|
|
"m03_s04_connectivity": 1,
|
|
"m03_s05_connectivity": 1,
|
|
"m03_s06_connectivity": 1,
|
|
"m03_s07_connectivity": 1,
|
|
"m03_s08_connectivity": 1,
|
|
"m03_s09_connectivity": 1,
|
|
"m03_s10_connectivity": 1,
|
|
"m03_s11_connectivity": 1,
|
|
"m03_s12_connectivity": 1,
|
|
"m03_s13_connectivity": 1,
|
|
"m03_s14_connectivity": 1,
|
|
"m03_s15_connectivity": 1,
|
|
"m04_s00_connectivity": 1,
|
|
"m04_s01_connectivity": 1,
|
|
"m04_s02_connectivity": 1,
|
|
"m04_s03_connectivity": 1,
|
|
"m04_s04_connectivity": 1,
|
|
"m04_s05_connectivity": 1,
|
|
"m04_s06_connectivity": 1,
|
|
"m04_s07_connectivity": 1,
|
|
"m04_s08_connectivity": 1,
|
|
"m04_s09_connectivity": 1,
|
|
"m04_s10_connectivity": 1,
|
|
"m04_s11_connectivity": 1,
|
|
"m04_s12_connectivity": 1,
|
|
"m04_s13_connectivity": 1,
|
|
"m04_s14_connectivity": 1,
|
|
"m04_s15_connectivity": 1,
|
|
"m05_s00_connectivity": 1,
|
|
"m05_s01_connectivity": 1,
|
|
"m05_s02_connectivity": 1,
|
|
"m05_s03_connectivity": 1,
|
|
"m05_s04_connectivity": 1,
|
|
"m05_s05_connectivity": 1,
|
|
"m05_s06_connectivity": 1,
|
|
"m05_s07_connectivity": 1,
|
|
"m05_s08_connectivity": 1,
|
|
"m05_s09_connectivity": 1,
|
|
"m05_s10_connectivity": 1,
|
|
"m05_s11_connectivity": 1,
|
|
"m05_s12_connectivity": 1,
|
|
"m05_s13_connectivity": 1,
|
|
"m05_s14_connectivity": 1,
|
|
"m05_s15_connectivity": 1,
|
|
"m06_s00_connectivity": 1,
|
|
"m06_s01_connectivity": 1,
|
|
"m06_s02_connectivity": 1,
|
|
"m06_s03_connectivity": 1,
|
|
"m06_s04_connectivity": 1,
|
|
"m06_s05_connectivity": 1,
|
|
"m06_s06_connectivity": 1,
|
|
"m06_s07_connectivity": 1,
|
|
"m06_s08_connectivity": 1,
|
|
"m06_s09_connectivity": 1,
|
|
"m06_s10_connectivity": 1,
|
|
"m06_s11_connectivity": 1,
|
|
"m06_s12_connectivity": 1,
|
|
"m06_s13_connectivity": 1,
|
|
"m06_s14_connectivity": 1,
|
|
"m06_s15_connectivity": 1,
|
|
"m07_s00_connectivity": 1,
|
|
"m07_s01_connectivity": 1,
|
|
"m07_s02_connectivity": 1,
|
|
"m07_s03_connectivity": 1,
|
|
"m07_s04_connectivity": 1,
|
|
"m07_s05_connectivity": 1,
|
|
"m07_s06_connectivity": 1,
|
|
"m07_s07_connectivity": 1,
|
|
"m07_s08_connectivity": 1,
|
|
"m07_s09_connectivity": 1,
|
|
"m07_s10_connectivity": 1,
|
|
"m07_s11_connectivity": 1,
|
|
"m07_s12_connectivity": 1,
|
|
"m07_s13_connectivity": 1,
|
|
"m07_s14_connectivity": 1,
|
|
"m07_s15_connectivity": 1,
|
|
"m08_s00_connectivity": 1,
|
|
"m08_s01_connectivity": 1,
|
|
"m08_s02_connectivity": 1,
|
|
"m08_s03_connectivity": 1,
|
|
"m08_s04_connectivity": 1,
|
|
"m08_s05_connectivity": 1,
|
|
"m08_s06_connectivity": 1,
|
|
"m08_s07_connectivity": 1,
|
|
"m08_s08_connectivity": 1,
|
|
"m08_s09_connectivity": 1,
|
|
"m08_s10_connectivity": 1,
|
|
"m08_s11_connectivity": 1,
|
|
"m08_s12_connectivity": 1,
|
|
"m08_s13_connectivity": 1,
|
|
"m08_s14_connectivity": 1,
|
|
"m08_s15_connectivity": 1,
|
|
"m09_s00_connectivity": 1,
|
|
"m09_s01_connectivity": 1,
|
|
"m09_s02_connectivity": 1,
|
|
"m09_s03_connectivity": 1,
|
|
"m09_s04_connectivity": 1,
|
|
"m09_s05_connectivity": 1,
|
|
"m09_s06_connectivity": 1,
|
|
"m09_s07_connectivity": 1,
|
|
"m09_s08_connectivity": 1,
|
|
"m09_s09_connectivity": 1,
|
|
"m09_s10_connectivity": 1,
|
|
"m09_s11_connectivity": 1,
|
|
"m09_s12_connectivity": 1,
|
|
"m09_s13_connectivity": 1,
|
|
"m09_s14_connectivity": 1,
|
|
"m09_s15_connectivity": 1,
|
|
"m10_s00_connectivity": 1,
|
|
"m10_s01_connectivity": 1,
|
|
"m10_s02_connectivity": 1,
|
|
"m10_s03_connectivity": 1,
|
|
"m10_s04_connectivity": 1,
|
|
"m10_s05_connectivity": 1,
|
|
"m10_s06_connectivity": 1,
|
|
"m10_s07_connectivity": 1,
|
|
"m10_s08_connectivity": 1,
|
|
"m10_s09_connectivity": 1,
|
|
"m10_s10_connectivity": 1,
|
|
"m10_s11_connectivity": 1,
|
|
"m10_s12_connectivity": 1,
|
|
"m10_s13_connectivity": 1,
|
|
"m10_s14_connectivity": 1,
|
|
"m10_s15_connectivity": 1,
|
|
"m11_s00_connectivity": 1,
|
|
"m11_s01_connectivity": 1,
|
|
"m11_s02_connectivity": 1,
|
|
"m11_s03_connectivity": 1,
|
|
"m11_s04_connectivity": 1,
|
|
"m11_s05_connectivity": 1,
|
|
"m11_s06_connectivity": 1,
|
|
"m11_s07_connectivity": 1,
|
|
"m11_s08_connectivity": 1,
|
|
"m11_s09_connectivity": 1,
|
|
"m11_s10_connectivity": 1,
|
|
"m11_s11_connectivity": 1,
|
|
"m11_s12_connectivity": 1,
|
|
"m11_s13_connectivity": 1,
|
|
"m11_s14_connectivity": 1,
|
|
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"m12_s00_connectivity": 1,
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|
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|
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|
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|
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"m15_s14_connectivity": 1,
|
|
"m15_s15_connectivity": 1,
|
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"component_name": "design_1_xbar_0",
|
|
"edk_iptype": "PERIPHERAL",
|
|
"c_baseaddr": 4096,
|
|
"c_highaddr": 5119
|
|
},
|
|
"ports": [
|
|
{
|
|
"role": "slave",
|
|
"target": "aurora_aurora_8b10b_ch0:USER_DATA_M_AXI_RX",
|
|
"name": "S00_AXIS"
|
|
},
|
|
{
|
|
"role": "master",
|
|
"target": "aurora_aurora_8b10b_ch0:USER_DATA_S_AXI_TX",
|
|
"name": "M00_AXIS"
|
|
},
|
|
{
|
|
"role": "slave",
|
|
"target": "aurora_aurora_8b10b_ch1:USER_DATA_M_AXI_RX",
|
|
"name": "S01_AXIS"
|
|
},
|
|
{
|
|
"role": "master",
|
|
"target": "aurora_aurora_8b10b_ch1:USER_DATA_S_AXI_TX",
|
|
"name": "M01_AXIS"
|
|
},
|
|
{
|
|
"role": "slave",
|
|
"target": "aurora_aurora_8b10b_ch2:USER_DATA_M_AXI_RX",
|
|
"name": "S02_AXIS"
|
|
},
|
|
{
|
|
"role": "master",
|
|
"target": "aurora_aurora_8b10b_ch2:USER_DATA_S_AXI_TX",
|
|
"name": "M02_AXIS"
|
|
},
|
|
{
|
|
"role": "slave",
|
|
"target": "aurora_aurora_8b10b_ch3:USER_DATA_M_AXI_RX",
|
|
"name": "S03_AXIS"
|
|
},
|
|
{
|
|
"role": "master",
|
|
"target": "aurora_aurora_8b10b_ch3:USER_DATA_S_AXI_TX",
|
|
"name": "M03_AXIS"
|
|
},
|
|
{
|
|
"role": "slave",
|
|
"target": "dma_pcie_axi_dma_0:MM2S",
|
|
"name": "S04_AXIS"
|
|
},
|
|
{
|
|
"role": "master",
|
|
"target": "dma_pcie_axi_dma_0:S2MM",
|
|
"name": "M04_AXIS"
|
|
},
|
|
{
|
|
"role": "slave",
|
|
"target": "dino_dinoif_fast_0:M00_AXIS",
|
|
"name": "S05_AXIS"
|
|
},
|
|
{
|
|
"role": "master",
|
|
"target": "dino_dinoif_dac_0:S00_AXIS",
|
|
"name": "M05_AXIS"
|
|
}
|
|
],
|
|
"num_ports": 6
|
|
},
|
|
"dino_axi_iic_0": {
|
|
"vlnv": "xilinx.com:ip:axi_iic:2.1",
|
|
"parameters": {
|
|
"c_family": "virtex7",
|
|
"c_s_axi_addr_width": 9,
|
|
"c_s_axi_data_width": 32,
|
|
"c_iic_freq": 100000,
|
|
"c_ten_bit_adr": 0,
|
|
"c_gpo_width": 1,
|
|
"c_s_axi_aclk_freq_hz": 125000000,
|
|
"c_scl_inertial_delay": 0,
|
|
"c_sda_inertial_delay": 0,
|
|
"c_sda_level": 1,
|
|
"c_smbus_pmbus_host": 0,
|
|
"c_disable_setup_violation_check": 0,
|
|
"c_static_timing_reg_width": 0,
|
|
"c_timing_reg_width": 32,
|
|
"c_default_value": 0,
|
|
"component_name": "design_1_axi_iic_0_0",
|
|
"ten_bit_adr": "7_bit",
|
|
"axi_aclk_freq_mhz": "125.0",
|
|
"iic_freq_khz": 100,
|
|
"use_board_flow": "false",
|
|
"iic_board_interface": "Custom",
|
|
"edk_iptype": "PERIPHERAL",
|
|
"c_baseaddr": 16384,
|
|
"c_highaddr": 17407
|
|
},
|
|
"irqs": {
|
|
"iic2intc_irpt": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:2"
|
|
}
|
|
},
|
|
"dino_dinoif_dac_0": {
|
|
"vlnv": "xilinx.com:module_ref:dinoif_dac:1.0",
|
|
"i2c_channel": 1,
|
|
"parameters": {
|
|
"component_name": "design_1_dinoif_dac_0_0",
|
|
"edk_iptype": "PERIPHERAL"
|
|
},
|
|
"ports": [
|
|
{
|
|
"role": "slave",
|
|
"target": "crossbar_axis_interconnect_0_xbar:M05_AXIS",
|
|
"name": "S00_AXIS"
|
|
}
|
|
]
|
|
},
|
|
"dino_dinoif_fast_0": {
|
|
"vlnv": "xilinx.com:module_ref:dinoif_fast:1.0",
|
|
"i2c_channel": 0,
|
|
"parameters": {
|
|
"component_name": "design_1_dinoif_fast_0_0",
|
|
"edk_iptype": "PERIPHERAL"
|
|
},
|
|
"ports": [
|
|
{
|
|
"role": "master",
|
|
"target": "crossbar_axis_interconnect_0_xbar:S05_AXIS",
|
|
"name": "M00_AXIS"
|
|
}
|
|
]
|
|
},
|
|
"dino_registerif_0": {
|
|
"vlnv": "xilinx.com:module_ref:registerif:1.0",
|
|
"parameters": {
|
|
"c_axi_data_width": 32,
|
|
"c_axi_addr_width": 32,
|
|
"component_name": "design_1_registerif_0_0",
|
|
"edk_iptype": "PERIPHERAL",
|
|
"c_baseaddr": 20480,
|
|
"c_highaddr": 21503
|
|
}
|
|
},
|
|
"dma_pcie_axi_dma_0": {
|
|
"vlnv": "xilinx.com:ip:axi_dma:7.1",
|
|
"parameters": {
|
|
"c_s_axi_lite_addr_width": 10,
|
|
"c_s_axi_lite_data_width": 32,
|
|
"c_dlytmr_resolution": 125,
|
|
"c_prmry_is_aclk_async": 0,
|
|
"c_enable_multi_channel": 0,
|
|
"c_num_mm2s_channels": 1,
|
|
"c_num_s2mm_channels": 1,
|
|
"c_include_sg": 1,
|
|
"c_sg_include_stscntrl_strm": 0,
|
|
"c_sg_use_stsapp_length": 0,
|
|
"c_sg_length_width": 14,
|
|
"c_m_axi_sg_addr_width": 32,
|
|
"c_m_axi_sg_data_width": 32,
|
|
"c_m_axis_mm2s_cntrl_tdata_width": 32,
|
|
"c_s_axis_s2mm_sts_tdata_width": 32,
|
|
"c_micro_dma": 0,
|
|
"c_include_mm2s": 1,
|
|
"c_include_mm2s_sf": 1,
|
|
"c_mm2s_burst_size": 16,
|
|
"c_m_axi_mm2s_addr_width": 32,
|
|
"c_m_axi_mm2s_data_width": 32,
|
|
"c_m_axis_mm2s_tdata_width": 32,
|
|
"c_include_mm2s_dre": 0,
|
|
"c_include_s2mm": 1,
|
|
"c_include_s2mm_sf": 1,
|
|
"c_s2mm_burst_size": 16,
|
|
"c_m_axi_s2mm_addr_width": 32,
|
|
"c_m_axi_s2mm_data_width": 32,
|
|
"c_s_axis_s2mm_tdata_width": 32,
|
|
"c_include_s2mm_dre": 0,
|
|
"c_increase_throughput": 0,
|
|
"c_family": "virtex7",
|
|
"component_name": "design_1_axi_dma_0_0",
|
|
"c_addr_width": 32,
|
|
"c_single_interface": 0,
|
|
"edk_iptype": "PERIPHERAL",
|
|
"c_baseaddr": 12288,
|
|
"c_highaddr": 13311
|
|
},
|
|
"memory-view": {
|
|
"M_AXI_SG": {
|
|
"dma_pcie_pcie_axi_pcie_0": {
|
|
"BAR0": {
|
|
"baseaddr": 0,
|
|
"highaddr": 4294967295,
|
|
"size": 4294967296
|
|
}
|
|
}
|
|
},
|
|
"M_AXI_MM2S": {
|
|
"dma_pcie_pcie_axi_pcie_0": {
|
|
"BAR0": {
|
|
"baseaddr": 0,
|
|
"highaddr": 4294967295,
|
|
"size": 4294967296
|
|
}
|
|
}
|
|
},
|
|
"M_AXI_S2MM": {
|
|
"dma_pcie_pcie_axi_pcie_0": {
|
|
"BAR0": {
|
|
"baseaddr": 0,
|
|
"highaddr": 4294967295,
|
|
"size": 4294967296
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"ports": [
|
|
{
|
|
"role": "master",
|
|
"target": "crossbar_axis_interconnect_0_xbar:S04_AXIS",
|
|
"name": "MM2S"
|
|
},
|
|
{
|
|
"role": "slave",
|
|
"target": "crossbar_axis_interconnect_0_xbar:M04_AXIS",
|
|
"name": "S2MM"
|
|
}
|
|
],
|
|
"irqs": {
|
|
"mm2s_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:0",
|
|
"s2mm_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1"
|
|
}
|
|
},
|
|
"dma_pcie_pcie_axi_pcie_0": {
|
|
"vlnv": "xilinx.com:ip:axi_pcie:2.9",
|
|
"parameters": {
|
|
"c_family": "virtex7",
|
|
"c_instance": "design_1_axi_pcie_0_1",
|
|
"c_s_axi_id_width": 2,
|
|
"c_s_axi_addr_width": 32,
|
|
"c_s_axi_data_width": 64,
|
|
"c_m_axi_addr_width": 32,
|
|
"c_m_axi_data_width": 64,
|
|
"c_no_of_lanes": 1,
|
|
"c_max_link_speed": 1,
|
|
"c_pcie_use_mode": "3.0",
|
|
"c_device_id": 28705,
|
|
"c_vendor_id": 4334,
|
|
"c_class_code": 360448,
|
|
"c_ref_clk_freq": 0,
|
|
"c_rev_id": 0,
|
|
"c_subsystem_id": 7,
|
|
"c_subsystem_vendor_id": 4334,
|
|
"c_pcie_cap_slot_implemented": 0,
|
|
"c_slot_clock_config": "TRUE",
|
|
"c_msi_decode_enable": "TRUE",
|
|
"c_int_fifo_depth": 0,
|
|
"c_num_msi_req": 4,
|
|
"c_interrupt_pin": 0,
|
|
"c_comp_timeout": 0,
|
|
"c_include_rc": 0,
|
|
"c_s_axi_supports_narrow_burst": 0,
|
|
"c_include_baroffset_reg": 1,
|
|
"c_axibar_num": 1,
|
|
"c_axibar2pciebar_0": 0,
|
|
"c_axibar2pciebar_1": 0,
|
|
"c_axibar2pciebar_2": 0,
|
|
"c_axibar2pciebar_3": 0,
|
|
"c_axibar2pciebar_4": 0,
|
|
"c_axibar2pciebar_5": 0,
|
|
"c_axibar_as_0": 0,
|
|
"c_axibar_as_1": 0,
|
|
"c_axibar_as_2": 0,
|
|
"c_axibar_as_3": 0,
|
|
"c_axibar_as_4": 0,
|
|
"c_axibar_as_5": 0,
|
|
"c_axibar_0": 0,
|
|
"c_axibar_highaddr_0": 4294967295,
|
|
"c_axibar_1": 4294967295,
|
|
"c_axibar_highaddr_1": 0,
|
|
"c_axibar_2": 4294967295,
|
|
"c_axibar_highaddr_2": 0,
|
|
"c_axibar_3": 4294967295,
|
|
"c_axibar_highaddr_3": 0,
|
|
"c_axibar_4": 4294967295,
|
|
"c_axibar_highaddr_4": 0,
|
|
"c_axibar_5": 4294967295,
|
|
"c_axibar_highaddr_5": 0,
|
|
"c_pciebar_num": 1,
|
|
"c_pciebar_as": 0,
|
|
"c_pciebar_len_0": 20,
|
|
"c_pciebar2axibar_0": 0,
|
|
"c_pciebar2axibar_0_sec": 1,
|
|
"c_pciebar_len_1": 16,
|
|
"c_pciebar2axibar_1": 4294967295,
|
|
"c_pciebar2axibar_1_sec": 1,
|
|
"c_pciebar_len_2": 16,
|
|
"c_pciebar2axibar_2": 4294967295,
|
|
"c_pciebar2axibar_2_sec": 1,
|
|
"c_pcie_blk_locn": 3,
|
|
"c_xlnx_ref_board": "VC707",
|
|
"pcie_ext_clk": "FALSE",
|
|
"pcie_ext_gt_common": "FALSE",
|
|
"ext_ch_gt_drp": "FALSE",
|
|
"shared_logic_in_core": "false",
|
|
"transceiver_ctrl_status_ports": "FALSE",
|
|
"ext_pipe_interface": "FALSE",
|
|
"c_device": "xc7vx485t",
|
|
"c_speed": -2,
|
|
"axi_aclk_loopback": "false",
|
|
"no_slv_err": "false",
|
|
"c_rp_bar_hide": "FALSE",
|
|
"enable_jtag_dbg": "false",
|
|
"c_axibar_chk_slv_err": "false",
|
|
"reduce_oob_freq": "false",
|
|
"component_name": "design_1_axi_pcie_0_1",
|
|
"include_rc": "PCI_Express_Endpoint_device",
|
|
"ref_clk_freq": "100_MHz",
|
|
"slot_clock_config": "true",
|
|
"pcie_use_mode": "GES_and_Production",
|
|
"no_of_lanes": "X1",
|
|
"max_link_speed": "5.0_GT/s",
|
|
"vendor_id": 4334,
|
|
"device_id": 28705,
|
|
"rev_id": 0,
|
|
"subsystem_vendor_id": 4334,
|
|
"subsystem_id": 7,
|
|
"enable_class_code": "true",
|
|
"class_code": 360448,
|
|
"base_class_menu": "Memory_controller",
|
|
"sub_class_interface_menu": "Other_memory_controller",
|
|
"bar0_enabled": "true",
|
|
"bar1_enabled": "false",
|
|
"bar2_enabled": "false",
|
|
"bar0_type": "Memory",
|
|
"bar1_type": "N/A",
|
|
"bar2_type": "N/A",
|
|
"bar0_scale": "Megabytes",
|
|
"bar1_scale": "N/A",
|
|
"bar2_scale": "N/A",
|
|
"bar0_size": 1,
|
|
"bar1_size": 8,
|
|
"bar2_size": 8,
|
|
"pciebar2axibar_0": 0,
|
|
"pciebar2axibar_1": 4294967295,
|
|
"pciebar2axibar_2": 4294967295,
|
|
"pciebar2axibar_1_sec": 1,
|
|
"pciebar2axibar_0_sec": 1,
|
|
"pciebar2axibar_2_sec": 1,
|
|
"interrupt_pin": "false",
|
|
"msi_decode_enabled": "true",
|
|
"num_msi_req": 4,
|
|
"int_fifo_depth": 16,
|
|
"comp_timeout": "50us",
|
|
"include_baroffset_reg": "true",
|
|
"axibar_as_0": "false",
|
|
"axibar_as_1": "false",
|
|
"axibar_as_2": "false",
|
|
"axibar_as_3": "false",
|
|
"axibar_as_4": "false",
|
|
"axibar_as_5": "false",
|
|
"axibar_1": 4294967295,
|
|
"axibar_2": 4294967295,
|
|
"axibar_3": 4294967295,
|
|
"axibar_4": 4294967295,
|
|
"axibar_5": 4294967295,
|
|
"axibar_highaddr_1": 0,
|
|
"axibar_highaddr_2": 0,
|
|
"axibar_highaddr_3": 0,
|
|
"axibar_highaddr_4": 0,
|
|
"axibar_highaddr_5": 0,
|
|
"axibar2pciebar_0": 0,
|
|
"axibar2pciebar_1": 0,
|
|
"axibar2pciebar_2": 0,
|
|
"axibar2pciebar_3": 0,
|
|
"axibar2pciebar_4": 0,
|
|
"axibar2pciebar_5": 0,
|
|
"baseaddr": 4096,
|
|
"highaddr": 8191,
|
|
"s_axi_id_width": 2,
|
|
"s_axi_addr_width": 32,
|
|
"s_axi_data_width": 64,
|
|
"m_axi_addr_width": 32,
|
|
"m_axi_data_width": 64,
|
|
"s_axi_supports_narrow_burst": "false",
|
|
"bar_64bit": "false",
|
|
"xlnx_ref_board": "VC707",
|
|
"pcie_blk_locn": "X1Y0",
|
|
"axibar_num": 1,
|
|
"en_ext_clk": "false",
|
|
"en_ext_gt_common": "false",
|
|
"en_ext_ch_gt_drp": "false",
|
|
"en_transceiver_status_ports": "false",
|
|
"en_ext_pipe_interface": "false",
|
|
"rp_bar_hide": "false",
|
|
"edk_iptype": "PERIPHERAL",
|
|
"axibar_0": 0,
|
|
"axibar_highaddr_0": 4294967295
|
|
},
|
|
"memory-view": {
|
|
"M_AXI": {
|
|
"axi_gpio_0": {
|
|
"Reg": {
|
|
"baseaddr": 0,
|
|
"highaddr": 127,
|
|
"size": 128
|
|
}
|
|
},
|
|
"crossbar_axis_interconnect_0_xbar": {
|
|
"Reg": {
|
|
"baseaddr": 4096,
|
|
"highaddr": 5119,
|
|
"size": 1024
|
|
}
|
|
},
|
|
"dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": {
|
|
"reg0": {
|
|
"baseaddr": 8192,
|
|
"highaddr": 9215,
|
|
"size": 1024
|
|
}
|
|
},
|
|
"dma_pcie_axi_dma_0": {
|
|
"Reg": {
|
|
"baseaddr": 12288,
|
|
"highaddr": 13311,
|
|
"size": 1024
|
|
}
|
|
},
|
|
"dino_axi_iic_0": {
|
|
"Reg": {
|
|
"baseaddr": 16384,
|
|
"highaddr": 17407,
|
|
"size": 1024
|
|
}
|
|
},
|
|
"dino_registerif_0": {
|
|
"reg0": {
|
|
"baseaddr": 20480,
|
|
"highaddr": 21503,
|
|
"size": 1024
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"axi_bars": {
|
|
"BAR0": {
|
|
"translation": 0,
|
|
"baseaddr": 0,
|
|
"highaddr": 4294967295,
|
|
"size": 4294967296
|
|
}
|
|
},
|
|
"pcie_bars": {
|
|
"BAR0": {
|
|
"translation": 0
|
|
}
|
|
}
|
|
},
|
|
"dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0": {
|
|
"vlnv": "xilinx.com:module_ref:axi_pcie_intc:1.0",
|
|
"parameters": {
|
|
"component_name": "design_1_axi_pcie_intc_0_0",
|
|
"edk_iptype": "PERIPHERAL",
|
|
"c_baseaddr": 8192,
|
|
"c_highaddr": 9215
|
|
}
|
|
}
|
|
}
|