mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
synced 2025-03-23 00:00:01 +01:00
a5b5e317d4
works and compiles so for. next is to implement different IP interfaces (Model, Interface, DataMover, Infrastructure, ...)
139 lines
3.1 KiB
JSON
139 lines
3.1 KiB
JSON
{
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"affinity": 1,
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"stats": 3,
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"name": "villas-acs",
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"logging": {
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"level": 5,
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"faciltities": [
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"path",
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"socket"
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],
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"file": "/var/log/villas-node.log",
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"syslog": true
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},
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"http": {
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"enabled": true,
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"htdocs": "/villas/web/socket/",
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"port": 80
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},
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"plugins": [
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"simple_circuit.so",
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"example_hook.so"
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],
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"fpgas": {
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"vc707": {
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"id": "10ee:7022",
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"slot": "03:00.0",
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"do_reset": true,
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"ips": {
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"axi_reset_0": {
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"vlnv": "xilinx.com:ip:axi_gpio:2.0",
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"baseaddr": 28672
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},
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"timer_0": {
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"vlnv": "xilinx.com:ip:axi_timer:2.0",
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"baseaddr": 16384,
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"irq": "axi_pcie_intc_0:0"
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},
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"dma_0": {
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"vlnv": "xilinx.com:ip:axi_dma:7.1",
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"baseaddr": 12288,
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"port": "switch_0:1",
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"irq": "axi_pcie_intc_0:3"
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},
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"axi_pcie_intc_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:1.0",
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"baseaddr": 45056
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},
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"dma_1": {
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"vlnv": "xilinx.com:ip:axi_dma:7.1",
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"baseaddr": 8192,
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"port": "switch_0:6",
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"irq": "axi_pcie_intc_0:3"
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},
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"fifo_mm_s_0": {
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"vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1",
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"baseaddr": 24576,
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"baseaddr_axi4": 49152,
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"port": "switch_0:2",
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"irq": "axi_pcie_intc_0:2"
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},
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"rtds_axis_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0",
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"baseaddr": 32768,
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"port": "switch_0:0",
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"irq": "axi_pcie_intc_0:5"
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},
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"hls_dft_0": {
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"vlnv": "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.0",
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"baseaddr": 36864,
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"port": "switch_0:5",
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"irq": "axi_pcie_intc_0:1",
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"period": 400,
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"harmonics": [
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0,
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1,
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3,
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5,
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7
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],
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"decimation": 0
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},
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"axis_data_fifo_0": {
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"vlnv": "xilinx.com:ip:axis_data_fifo:1.1",
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"port": "switch_0:3"
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},
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"switch_0": {
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"vlnv": "xilinx.com:ip:axis_interconnect:2.1",
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"baseaddr": 20480,
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"num_ports": 10,
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"paths": [
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{
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"in": "rtds_axis_0",
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"out": "dma_1",
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"reverse": true
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}
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]
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},
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"axis_data_fifo_1": {
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"vlnv": "xilinx.com:ip:axis_data_fifo:1.1",
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"port": "switch_0:6"
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}
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}
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}
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},
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"nodes": {
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"dma_0": {
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"type": "fpga",
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"datamover": "dma_0",
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"use_irqs": false
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},
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"dma_1": {
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"type": "fpga",
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"datamover": "dma_1",
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"use_irqs": false
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},
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"fifo_0": {
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"type": "fpga",
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"datamover": "fifo_mm_s_0",
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"use_irqs": false
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},
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"simple_circuit": {
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"type": "cbuilder",
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"model": "simple_circuit",
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"timestep": 2.5000000000000001e-5,
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"parameters": [
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1.0,
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0.001
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]
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}
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},
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"paths": [
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{
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"in": "dma_1",
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"out": "simple_circuit",
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"reverse": true
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}
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]
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}
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