mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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119 lines
2.8 KiB
C++
119 lines
2.8 KiB
C++
/** DMA driver
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*
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* @author Daniel Krebs <github@daniel-krebs.net>
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* @copyright 2018, RWTH Institute for Automation of Complex Power Systems (ACS)
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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******************************************************************************/
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/** @addtogroup fpga VILLASfpga
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* @{
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*/
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#pragma once
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#include <list>
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#include <string>
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#include <xilinx/xaxidma.h>
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#include "fpga/ip_node.hpp"
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#include "memory.hpp"
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namespace villas {
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namespace fpga {
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namespace ip {
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class Dma : public IpNode
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{
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public:
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friend class DmaFactory;
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bool init();
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bool reset();
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size_t write(const MemoryBlock& mem, size_t len);
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size_t read(const MemoryBlock& mem, size_t len);
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bool writeComplete()
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{ return hasScatterGather() ? writeCompleteSG() : writeCompleteSimple(); }
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bool readComplete()
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{ return hasScatterGather() ? readCompleteSG() : readCompleteSimple(); }
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bool pingPong(const MemoryBlock& src, const MemoryBlock& dst, size_t len);
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inline bool
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hasScatterGather() const
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{ return hasSG; }
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private:
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size_t writeSG(const void* buf, size_t len);
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size_t readSG(void* buf, size_t len);
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bool writeCompleteSG();
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bool readCompleteSG();
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size_t writeSimple(const void* buf, size_t len);
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size_t readSimple(void* buf, size_t len);
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bool writeCompleteSimple();
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bool readCompleteSimple();
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private:
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static constexpr char registerMemory[] = "Reg";
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static constexpr char mm2sInterrupt[] = "mm2s_introut";
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static constexpr char mm2sInterface[] = "M_AXI_MM2S";
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static constexpr char s2mmInterrupt[] = "s2mm_introut";
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static constexpr char s2mmInterface[] = "M_AXI_S2MM";
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// optional Scatter-Gather interface to access descriptors
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static constexpr char sgInterface[] = "M_AXI_SG";
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std::list<MemoryBlockName> getMemoryBlocks() const
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{ return { registerMemory }; }
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XAxiDma xDma;
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bool hasSG;
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};
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class DmaFactory : public IpNodeFactory {
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public:
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DmaFactory();
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IpCore* create()
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{ return new Dma; }
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std::string
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getName() const
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{ return "Dma"; }
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std::string
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getDescription() const
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{ return "Xilinx's AXI4 Direct Memory Access Controller"; }
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Vlnv getCompatibleVlnv() const
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{ return {"xilinx.com:ip:axi_dma:"}; }
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};
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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/** @} */
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