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109 lines
3.1 KiB
C++
109 lines
3.1 KiB
C++
/** FIFO unit test.
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*
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* @file
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <criterion/criterion.h>
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#include <villas/log.hpp>
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#include <villas/memory.hpp>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/ips/rtds2gpu.hpp>
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#include <villas/fpga/ips/switch.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include "global.hpp"
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static constexpr size_t SAMPLE_SIZE = 4;
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static constexpr size_t SAMPLE_COUNT = 8;
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static constexpr size_t FRAME_SIZE = SAMPLE_COUNT * SAMPLE_SIZE;
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Test(fpga, rtds2gpu, .description = "Rtds2Gpu")
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{
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auto logger = loggerGetOrCreate("unittest:rtds2gpu");
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for(auto& ip : state.cards.front()->ips) {
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if(*ip != villas::fpga::Vlnv("xilinx.com:hls:rtds2gpu:"))
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continue;
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logger->info("Testing {}", *ip);
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auto rtds2gpu = reinterpret_cast<villas::fpga::ip::Rtds2Gpu&>(*ip);
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auto dmaMem0 = villas::HostDmaRam::getAllocator(0).allocate<char>(FRAME_SIZE + 4);
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auto dmaMem1 = villas::HostDmaRam::getAllocator(0).allocate<char>(FRAME_SIZE + 4);
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// continue;
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auto axiSwitch = reinterpret_cast<villas::fpga::ip::AxiStreamSwitch*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("xilinx.com:ip:axis_switch:")));
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cr_assert_not_null(axiSwitch);
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auto dma = reinterpret_cast<villas::fpga::ip::Dma*>(
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state.cards.front()->lookupIp(villas::fpga::Vlnv("xilinx.com:ip:axi_dma:")));
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cr_assert_not_null(dma);
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memset(&dmaMem0, 0x55, dmaMem0.getMemoryBlock().getSize());
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memset(&dmaMem1, 0x11, dmaMem1.getMemoryBlock().getSize());
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puts("Before:");
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for(size_t i = 0; i < dmaMem0.getMemoryBlock().getSize(); i++) {
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printf("0x%02x ", dmaMem0[i]);
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}
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puts("");
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rtds2gpu.dump();
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cr_assert(axiSwitch->connect(7, 6));
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cr_assert(axiSwitch->connect(6, 7));
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cr_assert(rtds2gpu.startOnce(dmaMem0.getMemoryBlock(), SAMPLE_COUNT),
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"Preparing Rtds2Gpu IP failed");
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cr_assert(dma->write(dmaMem1.getMemoryBlock(), FRAME_SIZE));
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// cr_assert(axiSwitch->connect(6, 6)); // loopback
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// cr_assert(dma->read(dmaMem1.getMemoryBlock(), FRAME_SIZE));
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// cr_assert(dma->readComplete());
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cr_assert(dma->writeComplete());
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puts("After:");
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for(size_t i = 0; i < dmaMem0.getMemoryBlock().getSize(); i++) {
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printf("0x%02x ", dmaMem0[i]);
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}
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puts("");
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rtds2gpu.dump();
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cr_assert(rtds2gpu.isDone());
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logger->info(TXT_GREEN("Passed"));
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}
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}
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