Niklas Eiling d9b3bdb0de fpga: DMA: poll BD instead of hardware register ... polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways. Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>		2024-06-18 12:39:42 +02:00
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gpu	Use spaces for indention of C++ comments	2024-02-29 23:18:47 +01:00
include/villas/fpga	fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs	2024-06-18 12:39:42 +02:00
lib	fpga: DMA: poll BD instead of hardware register	2024-06-18 12:39:42 +02:00
src	Replace last tab indentation with spaces	2024-02-29 23:18:47 +01:00
tests/unit	Use spaces for indention of C++ comments	2024-02-29 23:18:47 +01:00
thirdparty	Reformat all code with clang-format	2024-02-29 19:34:27 +01:00
CMakeLists.txt	Use spaces for indention of CMake files	2024-02-29 23:18:47 +01:00
libvillas-fpga.pc.in	Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82)	2023-09-08 11:35:18 +02:00
past-commits.txt	Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82)	2023-09-08 11:35:18 +02:00