e20bcd3d1e
This setting improves latency by remove various checks. Use with caution! Requires read cache in FPGA design! The common use case in VILLASfpga is that we have exactly one write for every read and the number of exchanged signals do not change. If this is the case, we can reuse the buffer descriptors during reads and write, thus avoidng freeing, reallocating and setting them up. We set up the descriptors in start, and in write or read, we only reset the complete bit in the buffer descriptor and write to the tdesc register to start the DMA transfer. Improves read/write latency by approx. 40%. Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de> |
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| .devcontainer | ||
| .reuse | ||
| clients | ||
| cmake | ||
| common | ||
| doc | ||
| etc | ||
| fpga | ||
| include/villas | ||
| lib | ||
| LICENSES | ||
| lua/hooks | ||
| packaging | ||
| plugins | ||
| python | ||
| src | ||
| tests | ||
| tools | ||
| web | ||
| .clang-format | ||
| .clangd | ||
| .dockerignore | ||
| .editorconfig | ||
| .envrc | ||
| .git-blame-ignore-revs | ||
| .gitignore | ||
| .gitlab-ci.yml | ||
| .gitmodules | ||
| .mailmap | ||
| CMakeLists.txt | ||
| CODEOWNERS | ||
| CONTRIBUTING.md | ||
| flake.lock | ||
| flake.nix | ||
| LICENSE | ||
| README.md | ||
VILLASnode
This is VILLASnode, a gateway for processing and forwardning simulation data between real-time simulators. VILLASnode is a client/server application to connect simulation equipment and software such as:
- OPAL-RT RT-LAB,
- RTDS GTFPGA cards,
- RTDS GTWIF cards,
- Simulink,
- LabView,
- and FPGA models
by using protocols such as:
- IEEE 802.2 Ethernet / IP / UDP,
- ZeroMQ & nanomsg,
- MQTT & AMQP
- WebSockets
- Shared Memory
- Files
- IEC 61850 Sampled Values / GOOSE
- Analog/Digital IO via Comedi drivers
- Infiniband (ibverbs)
It's designed with a focus on very low latency to achieve real-time exchange of simulation data. VILLASnode is used in distributed- and co-simulation scenarios and developed for the field of power grid simulation at the EON Energy Research Center in Aachen, Germany.
Documentation
User documentation is available here: https://villas.fein-aachen.org/docs/
Related Projects
License
This project is released under the terms of the Apache 2.0 license.
We kindly ask all academic publications employing components of VILLASframework to cite one of the following papers:
- A. Monti et al., "A Global Real-Time Superlab: Enabling High Penetration of Power Electronics in the Electric Grid," in IEEE Power Electronics Magazine, vol. 5, no. 3, pp. 35-44, Sept. 2018.
- S. Vogel, M. Mirz, L. Razik and A. Monti, "An open solution for next-generation real-time power system simulation," 2017 IEEE Conference on Energy Internet and Energy System Integration (EI2), Beijing, 2017, pp. 1-6.
For other licensing options please consult Prof. Antonello Monti.
- SPDX-FileCopyrightText: 2014-2023 Institute for Automation of Complex Power Systems, RWTH Aachen University
- SPDX-FileCopyrightText: 2023 OPAL-RT Germany GmbH
- SPDX-FileCopyrightText: 2022-2023 Niklas Eiling niklas.eiling@eonerc.rwth-aachen.de
- SPDX-FileCopyrightText: 2018-2023 Steffen Vogel post@steffenvogel.de
- SPDX-FileCopyrightText: 2018 Daniel Krebs dkrebs@eonerc.rwth-aachen.de
- SPDX-License-Identifier: Apache-2.0
Contact
- Steffen Vogel post@steffenvogel.de
- Niklas Eiling niklas.eiling@eonerc.rwth-aachen.de
- Felix Wege fwege@eonerc.rwth-aachen.de
- Alexandra Bach alexandra.bach@eonerc.rwth-aachen.de
Institute for Automation of Complex Power Systems (ACS) EON Energy Research Center (EONERC) RWTH University Aachen, Germany