mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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131 lines
3.1 KiB
C++
131 lines
3.1 KiB
C++
/** FIFO related helper functions
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*
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* These functions present a simpler interface to Xilinx' FIFO driver (XLlFifo_*)
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @author Daniel Krebs <github@daniel-krebs.net>
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* @copyright 2017-2018, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <unistd.h>
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#include <xilinx/xstatus.h>
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#include <xilinx/xllfifo.h>
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#include <villas/fpga/ips/fifo.hpp>
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#include <villas/fpga/ips/intc.hpp>
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namespace villas {
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namespace fpga {
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namespace ip {
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// instantiate factory to make available to plugin infrastructure
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static FifoFactory factory;
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static FifoDataFactory factoryData;
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FifoFactory::FifoFactory() :
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IpNodeFactory(getName())
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{
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// nothing to do
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}
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FifoDataFactory::FifoDataFactory() :
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IpNodeFactory(getName())
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{
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// nothing to do
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}
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bool Fifo::init()
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{
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XLlFifo_Config fifo_cfg;
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try {
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// if this throws an exception, then there's no AXI4 data interface
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fifo_cfg.Axi4BaseAddress = getBaseAddr(axi4Memory);
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fifo_cfg.Datainterface = 1;
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} catch(const std::out_of_range&) {
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fifo_cfg.Datainterface = 0;
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}
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if (XLlFifo_CfgInitialize(&xFifo, &fifo_cfg, getBaseAddr(registerMemory)) != XST_SUCCESS)
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return false;
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if(irqs.find(irqName) == irqs.end()) {
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logger->error("IRQ '{}' not found but required", irqName);
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return false;
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}
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// Receive complete IRQ
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XLlFifo_IntEnable(&xFifo, XLLF_INT_RC_MASK);
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irqs[irqName].irqController->enableInterrupt(irqs[irqName], false);
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return true;
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}
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bool Fifo::stop()
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{
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// Receive complete IRQ
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XLlFifo_IntDisable(&xFifo, XLLF_INT_RC_MASK);
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irqs[irqName].irqController->disableInterrupt(irqs[irqName]);
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return true;
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}
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size_t Fifo::write(const void *buf, size_t len)
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{
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uint32_t tdfv;
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tdfv = XLlFifo_TxVacancy(&xFifo);
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if (tdfv < len)
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return -1;
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// buf has to be re-casted because Xilinx driver doesn't use const
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XLlFifo_Write(&xFifo, (void*) buf, len);
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XLlFifo_TxSetLen(&xFifo, len);
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return len;
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}
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size_t Fifo::read(void *buf, size_t len)
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{
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size_t nextlen = 0;
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size_t rxlen;
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while (!XLlFifo_IsRxDone(&xFifo))
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irqs[irqName].irqController->waitForInterrupt(irqs[irqName]);
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XLlFifo_IntClear(&xFifo, XLLF_INT_RC_MASK);
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/* Get length of next frame */
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rxlen = XLlFifo_RxGetLen(&xFifo);
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nextlen = std::min(rxlen, len);
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/* Read from FIFO */
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XLlFifo_Read(&xFifo, buf, nextlen);
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return nextlen;
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}
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} // namespace ip
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} // namespace fpga
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} // namespace villas
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