mirror of
https://git.rwth-aachen.de/acs/public/villas/node/
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77 lines
1.6 KiB
C++
77 lines
1.6 KiB
C++
/** Communicate with VILLASfpga Xilinx FPGA boards
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*
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* @file
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* @author Steffen Vogel <svogel2@eonerc.rwth-aachen.de>
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* @copyright 2014-2022, Institute for Automation of Complex Power Systems, EONERC
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* @license Apache 2.0
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*********************************************************************************/
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#pragma once
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#include <villas/node/config.hpp>
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#include <villas/format.hpp>
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#include <villas/timing.hpp>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/node.hpp>
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#include <villas/fpga/ips/dma.hpp>
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namespace villas {
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namespace node {
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/* Forward declarations */
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class NodeCompat;
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using namespace villas;
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#define FPGA_DMA_VLNV
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#define FPGA_AURORA_VLNV "acs.eonerc.rwth-aachen.de:user:aurora_axis:"
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struct fpga_node {
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int irqFd;
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int coalesce;
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bool polling;
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std::shared_ptr<fpga::PCIeCard> card;
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std::shared_ptr<fpga::ip::Dma> dma;
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std::shared_ptr<fpga::ip::Node> intf;
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struct {
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struct {
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MemoryAccessor<int32_t> i;
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MemoryAccessor<float> f;
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} accessor;
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MemoryBlock::Ptr block;
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} in, out;
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// Config only
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std::string cardName;
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std::string intfName;
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std::string dmaName;
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};
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int fpga_type_start(SuperNode *sn);
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int fpga_type_stop();
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int fpga_init(NodeCompat *n);
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int fpga_destroy(NodeCompat *n);
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int fpga_parse(NodeCompat *n, json_t *json);
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char * fpga_print(NodeCompat *n);
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int fpga_check(NodeCompat *n);
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int fpga_prepare(NodeCompat *n);
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int fpga_write(NodeCompat *n, struct Sample * const smps[], unsigned cnt);
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int fpga_read(NodeCompat *n, struct Sample * const smps[], unsigned cnt);
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int fpga_poll_fds(NodeCompat *n, int fds[]);
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} /* namespace node */
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} /* namespace villas */
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