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30 lines
No EOL
918 B
C
30 lines
No EOL
918 B
C
/** Hardcoded configuration for VILLASfpga
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2015-2016, Steffen Vogel
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* This file is part of VILLASnode. All Rights Reserved. Proprietary and confidential.
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* Unauthorized copying of this file, via any medium is strictly prohibited.
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**********************************************************************************/
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#ifndef _CONFIG_FPGA_H_
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#define _CONFIG_FPGA_H_
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#define AFFINITY (1 << 3)
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#define PRIORITY 90
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#define RTDS_DM_FIFO 1
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#define RTDS_DM_DMA_SIMPLE 2
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#define RTDS_DM_DMA_SG 3
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#define DATAMOVER RTDS_DM_DMA_SIMPLE
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/** PCIe BAR number of VILLASfpga registers */
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#define PCI_BAR 0
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/** AXI Bus frequency for all components
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* except RTDS AXI Stream bridge which runs at RTDS_HZ (100 Mhz) */
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#define AXI_HZ 125000000 // 125 MHz
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#define PCI_VID_XILINX 0x10ee
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#define PCI_PID_VFPGA 0x7022
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#endif /* _CONFIG_FPGA_H_ */ |