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98 lines
2.9 KiB
C++
98 lines
2.9 KiB
C++
/** RTDS AXI-Stream RTT unit test.
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*
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* @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
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* @copyright 2017-2018, Steffen Vogel
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* @license GNU General Public License (version 3)
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*
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* VILLASfpga
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*********************************************************************************/
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#include <criterion/criterion.h>
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#include <villas/fpga/card.hpp>
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#include <villas/fpga/vlnv.hpp>
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#include <villas/fpga/ips/dma.hpp>
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#include <villas/fpga/ips/switch.hpp>
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#include <villas/fpga/ips/rtds.hpp>
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extern struct fpga_card *card;
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// cppcheck-suppress unknownMacro
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Test(fpga, rtds_rtt, .description = "RTDS: tight rtt")
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{
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int ret;
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struct fpga_ip *ip, *rtds;
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struct dma_mem buf;
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size_t recvlen;
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std::list<villas::fpga::ip::Rtds*> rtdsIps;
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std::list<villas::fpga::ip::Dma*> dmaIps;
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/* Get IP cores */
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for (auto &ip : state.cards.front()->ips) {
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if (*ip == villas::fpga::Vlnv("acs.eonerc.rwth-aachen.de:user:rtds_axis:")) {
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auto rtds = reinterpret_cast<villas::fpga::ip::Rtds*>(ip.get());
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rtdsIps.push_back(rtds);
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}
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if (*ip == villas::fpga::Vlnv("xilinx.com:ip:axi_dma:")) {
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auto dma = reinterpret_cast<villas::fpga::ip::Dma*>(ip.get());
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dmaIps.push_back(dma);
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}
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}
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for (auto rtds : rtdsIps) {
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for (auto dma : dmaIps) {
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rtds->connect
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}
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}
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ret = switch_connect(card->sw, rtds, ip);
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cr_assert_eq(ret, 0, "Failed to configure switch");
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ret = switch_connect(card->sw, ip, rtds);
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cr_assert_eq(ret, 0, "Failed to configure switch");
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ret = dma_alloc(ip, &buf, 0x100, 0);
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cr_assert_eq(ret, 0, "Failed to allocate DMA memory");
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while (1) {
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ret = dma_read(ip, buf.base_phys, buf.len);
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cr_assert_eq(ret, 0, "Failed to start DMA read: %d", ret);
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ret = dma_read_complete(ip, NULL, &recvlen);
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cr_assert_eq(ret, 0, "Failed to complete DMA read: %d", ret);
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ret = dma_write(ip, buf.base_phys, recvlen);
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cr_assert_eq(ret, 0, "Failed to start DMA write: %d", ret);
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ret = dma_write_complete(ip, NULL, NULL);
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cr_assert_eq(ret, 0, "Failed to complete DMA write: %d", ret);
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}
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ret = switch_disconnect(card->sw, rtds, ip);
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cr_assert_eq(ret, 0, "Failed to configure switch");
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ret = switch_disconnect(card->sw, ip, rtds);
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cr_assert_eq(ret, 0, "Failed to configure switch");
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ret = dma_free(ip, &buf);
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cr_assert_eq(ret, 0, "Failed to release DMA memory");
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}
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